CMPE 691: Advanced Topics - Configurable System Design
Spring 2018

Course Information

Course Readings/ Tutorials

Paper/Tutorial Comments
Downloading and Installng ISE 14.7, Licence and Bug Fix Instructions to Install ISE 14.7, Licence and Bug Fix
ISE 14.7 and configuration for Nexys FPGA board Instructions for creating projects in Xilinx ISE 14.7 and Artix-7 board
counter example Download the file and generate the .bit file through xilinx ISE Project Navigator flow to program the Artix-7 FPGA.
A simple tutorial for Verilog module creation and Isim Simulator Verilog example files Eight_Bit_Mu ltiplier.v , Eight_Bit_Multiplier_ tb.v
 **VGA Rectangle on Artix  Initial code for showing a rectangle using VGA
Nexys4 Board with Artix-7 User Guide and UCF file You need to read this in order to know the FPGA pins locations for LED, switches and clock.
Quick reference for verilog Helpful and handy verilog reference.
Verilog according to Tom Helpful intro to verilog. Please also read the accompanying notes.
Isim Simulator Steps for running Isim simulator, with Verilog example files nand_latch.v , nand_latch_tb.v .
Isim Simulator User Manual Complete Xilinx user manual for Isim simulator .

Homework / Projects

All future dates tentative until hwk/project assigned.

Number Due Date % Hwk/proj grade Material covered and addiotional files
 1   Feb. 16,11 pm 10% Binary arithmetic and conversion, verilog, and multi-input adders, result report example testbench template
 2   Phase1 Testbench simulation and demo Mar 4th, Phase 2 Hardware demo March 11   11pm %20 State machine, and image color change and VGA imageRGB2BW.m picture_to_matrix.m parrot128.png
 3   Phase 1 ISE Mar 28th and Phase 2 Vivado Apr3rd  , 11 pm 15% State machines, timing, slice count and power analysis, memory and state machine, FIFOs
 4  Phase 1, April 24, 1 pm, Matlab simulation, characterization of algorithm and hardware arachitecture and block diagram design. Phase 2: May 1st , Details of hardware design Phase 3: May 8th, Simulations of different kernels Phase Final: May 15th, VGA Hardware demo and Final presentation, Final report **FINAL REPORT must be in IEEE two column conference format.

Course Topics and Lecture Slides

Future details are tentative.

Date Lecture Topics
01/30/2018/ Introduction Course introduction.
02/01/2018/ Verilog 1 Verilog example and sytles, refer to tutorials for more information and sample verilog
02/01/2018 Design and Verilog Module Verilog Module
02/06/2018 Sign Extension Number representation, sign extension
02/06/2018 Fixed-point Number Fixedpoint number reprsentation
02/08/2018 Floating Point Floating point.
02/15/2018 Numeric Basics Slides from reference book along with Verilog examples (covers numeric basics, Adders, Multi-input adder)
02/15/2018 Adder subtractor Adder/Subtractor, Multiplier Circuits and Verilog implementation.
02/15/2018 Verilog Testing Verilog testbench
02/06/2018 More verilog examples Quiz example, Blocking non Blocking, arrhythmetic shift
02/20/2018 Squaring Squaring.
02/20/2018 Fixed Input Mults Multipliers.
02/20/2018 Memories Overview of memories and implementation.
02/22/2018 Blocking nonblocking statement >More Verilog Examples, Blocking nonblocking statement
02/27/2018 Sequential Basics and pipelining Sequential Basics and Pipelining
02/27/2018 Verilog 2 Register, reset and enable signals modeling in registers
03/01/2018 State Machines State machines.
03/01/2018 testbench for the sequential multiplier testbench for the sequential multiplier
03/06/2018 Memory Examples and FIFO Examples and FIFO.
03/08/2018 FPGA Architectures FPGA Comparison with ASIC and DSP Implementation.
03/08/2018 FPGA Design Flow FPGA device utilization, timing constraints, and memory.
03/08/2018 Pipelining & Latency Pipelining & Latency
03/13/2018 FPGAs 3 More on Timing Constraints, FFs and latches
03/13/2018 ISE Synthesis and Place and Route Options ISE Synthesis and Place and Route Options
03/15/2018 Xilinx Xpower Analyzer Overview of Power consumption measurement and Xpower Analyzer
03/13/2018 Xilinx IP Core IPCore and Xilinx IP core generator
Notes on UART interface Xilinx UART interface
Xilinx Manual on UART Xilinx UART manual.
Serial interface Example for FFT Serial Transmission example design files Serial interface Example for FFT block diagram and design files for practice.
Deep learning Intro to Deep learning (source: Nvidia)
convolution image Convolution image filter
Convolutional networks Convolutional networks
KNN algorithm and simulation KNN algorithm, EEG database and simulation setup
fixedpoint conversion in matlab fixedpoint conversion in matlab.
Saturation Overview of Saturation in Verilog.
Rounding Overview of Rounding in Verilog.
K Nearest Neighbor Algorithm Introduction K nearest neighbor algorithm and an example.