Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/vga_tb |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserBrowsedStrategyFiles=C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2017-02-22T12:34:10 |
PROP_intWbtProjectID=26E7DAF7F1FB4446B3A75EE9914EB659 |
PROP_intWbtProjectIteration=26 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.vga_tb |
PROP_AutoTop=true |
PROP_DevFamily=Artix7 |
PROP_DevDevice=xc7a100t |
PROP_DevFamilyPMName=artix7 |
PROP_DevPackage=csg324 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-1 |
PROP_PreferredLanguage=Verilog |
FILE_UCF=1 |
FILE_VERILOG=4 |