vgaProject Project Status (02/23/2017 - 21:41:31)
Project File: vga_2.xise Parser Errors: No Errors
Module Name: vgaProject Implementation State: Programming File Generated
Target Device: xc7a100t-1csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
14 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 85 126,800 1%  
    Number used as Flip Flops 85      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 277 63,400 1%  
    Number used as logic 272 63,400 1%  
        Number using O6 output only 77      
        Number using O5 output only 70      
        Number using O5 and O6 125      
        Number used as ROM 0      
    Number used as Memory 0 19,000 0%  
    Number used exclusively as route-thrus 5      
        Number with same-slice register load 0      
        Number with same-slice carry load 5      
        Number with other load 0      
Number of occupied Slices 95 15,850 1%  
Number of LUT Flip Flop pairs used 277      
    Number with an unused Flip Flop 192 277 69%  
    Number with an unused LUT 0 277 0%  
    Number of fully used LUT-FF pairs 85 277 30%  
    Number of unique control sets 8      
    Number of slice register sites lost
        to control set restrictions
35 126,800 1%  
Number of bonded IOBs 29 210 13%  
    Number of LOCed IOBs 29 29 100%  
Number of RAMB36E1/FIFO36E1s 0 135 0%  
Number of RAMB18E1/FIFO18E1s 0 270 0%  
Number of BUFG/BUFGCTRLs 3 32 9%  
    Number used as BUFGs 3      
    Number used as BUFGCTRLs 0      
Number of IDELAYE2/IDELAYE2_FINEDELAYs 0 300 0%  
Number of ILOGICE2/ILOGICE3/ISERDESE2s 0 300 0%  
Number of ODELAYE2/ODELAYE2_FINEDELAYs 0      
Number of OLOGICE2/OLOGICE3/OSERDESE2s 0 300 0%  
Number of PHASER_IN/PHASER_IN_PHYs 0 24 0%  
Number of PHASER_OUT/PHASER_OUT_PHYs 0 24 0%  
Number of BSCANs 0 4 0%  
Number of BUFHCEs 0 96 0%  
Number of BUFRs 0 24 0%  
Number of CAPTUREs 0 1 0%  
Number of DNA_PORTs 0 1 0%  
Number of DSP48E1s 0 240 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of IBUFDS_GTE2s 0 4 0%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 0 6 0%  
Number of IN_FIFOs 0 24 0%  
Number of MMCME2_ADVs 0 6 0%  
Number of OUT_FIFOs 0 24 0%  
Number of PCIE_2_1s 0 1 0%  
Number of PHASER_REFs 0 6 0%  
Number of PHY_CONTROLs 0 6 0%  
Number of PLLE2_ADVs 0 6 0%  
Number of STARTUPs 0 1 0%  
Number of XADCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.31      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Feb 23 21:38:53 2017014 Warnings (0 new)0
Translation ReportCurrentThu Feb 23 21:39:03 2017000
Map ReportCurrentThu Feb 23 21:39:35 2017005 Infos (0 new)
Place and Route ReportCurrentThu Feb 23 21:39:58 2017003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentThu Feb 23 21:40:15 2017004 Infos (0 new)
Bitgen ReportCurrentThu Feb 23 21:41:27 2017001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateWed Feb 22 14:14:55 2017
WebTalk ReportOut of DateThu Feb 23 21:41:27 2017
WebTalk Log FileOut of DateThu Feb 23 21:41:31 2017

Date Generated: 02/23/2017 - 21:43:06