CMPE 641: Topics in VLSI
Spring 2016

Course Information

Course Readings/ Tutorials

Paper/Tutorial Comments
8-bit Multiplier, Eight_Bit_Multiplier_tb.v Verilog example and tesbench for 8-bit mulitiplier with sign extension of the inputs in verilog
8-bit multiplier example A simple verilog module for 8-bit multiplier behaviour without sign extension of inputs in verilog
counter with enable Verilog file for counter example
Quick reference for verilog Helpful and handy verilog reference.
Verilog according to Tom Helpful intro to verilog.
cadence setup steps Follow the steps to setup your account to use cadence tool, Ignore the first that talks about ITE 375 labs, that's already setup.
NCverilog tutorial Tutorial for ncverilog and ncsim for simulation,verilog file for dff.
rc command reference Command reference for rc compiler

Homework / Projects

All future dates tentative until hwk/project assigned.

Number Due Date % Hwk/proj grade Material covered and addiotional files
 1   Feb 18th  1 pm 14% Arithmentic Logic Unit (ALU) design in verilog with 7 different functions and test with ncverilog, example for testbench.
 2   March 3rd  1 pm 14% Synthesis and characterisation of a few digital circuits interms of logic gate area, power and speed RC compiler script and files hierarchy.
 3   March 26rd  11 pm 14% Memory (Arm core generator and verilog) design, State machine, Synthesis logic gate area, power and speed
 4   April 12th  1 pm 14% Designing standard cells
 3   Apr 21st  11 pm 14% Cadence Encounter Place and route for ALU. Report area, power and speed

Course Topics and Lecture Slides

Future details are tentative.

Date Lecture Topics
01/28/2016 Introduction Syllabus and course overview and applications
02/02/2016 Digital ASIC flow Digital ASIC flow
02/04/2016 Digital ASIC flow Digital ASIC flow-continue
02/09/2016 Verilog 1 Verilog
02/09/2016 Sign Extension Number representation & Sign extension.
02/11/2016 More verilog examples Quiz example, Blocking non Blocking, arrhythmetic shift
02/11/2016 Verilog Testing Verilog testbench
02/04/2016 FPGA vs ASIC Design flow FPGA vs ASIC chip design flow
02/09/2016 ASIC design flow ASIC design flow
02/11/2016 Standard Cell Libraries Lab 1 announced, Standard Cell Libraries, design, characteristics, generation of different views,
02/18/2016 standard cells standard cells, rulles
02/23/2016 Abstract generation Standard cells and abstract generation
02/18/2016 Sequential Basics & Pipelining Overview of Sequential Logic & Pipelines
02/23/2016 Pipelining & Latency Pipelining & Latency
02/23/2016 Synthesis flow and adding constraints Synthesis flow, slides courtesy of Drs. Markovic and Tarighat
02/25/2016 rc compiler rc compiler description for multiplier example lab2. For more details on commands refer to rc command reference and rc synthsis flow that are in your directory
03/07/2016 State Machines State machines.
03/10/2016 ARM memory generator Tutorial on ARM memory generator and synthsis
03/10/2016 Memories Overview of memories and implementation.
Memory Examples and FIFO Examples and FIFO.
03/03/2016 State Machines State machines.
03/08/2016 LEF, DEF files Different design formats LEF, DEF files
04/10/2016 place and route using Encounter GUI Helpful slides on using Cadence Encounter (slides from )
04/10/2016 place and route using Encounter GUI Helpful tutorial on using Cadence Encounter (from UT Dallas Dr. Sechen)
04/10/2016 place and route using Encounter GUI Helpful tutorial on using Cadence Encounter (from UT Dallas Dr. Sechen)