Final Study Guide

Memory Systems

  1. What is the difference between temporal and spatial locality? How are different memory systems designed to take advantage of localities?
  2. Why is a processor stalled when reading from memory?
  3. With respect to caches, define the terms index, tag, valid bit, and set.
  4. Given a cache design, be able to calculate to which index / set a physical address maps (Lecture 18, slide 18 and also Lecture 19, slide 9).
  5. Given a physical address size and a cache design, be able to calculate how large the cache needs to be (Lecture 18, slide 20 and also Lecture 19, slide 12)
  6. What is the difference between data and instruction caches?
  7. When should one use a write back versus write through policy? When should caching be outright disabled?
  8. What is the difference between inclusive and exclusive cache policies?
  9. How does a cache timing attack work?
  10. Be able to calculate how many page table entries are needed, and how large a page table entry is (Lecture 21, slides 13 and 15)
  11. Understand how TLBs are used by the MMU (Lecture 21, slides 20 and 21)
  12. Given an x86-64 virtual address, how does the MMU calculate the physical address?

I/O Handling

  1. What is the difference between physical, virtual, and bus addresses? For each type of address, name a device that uses that addressing scheme.
  2. Why does port I/O exist? Why does memory-mapped I/O exist?
  3. What values are stored within a DMA TxD?
  4. Given spinning hard drive characteristics, be able to calculate its average access time (Lecture 23, slide 13).
  5. Given a Hamming code, be able to calculate the corrected value (Lecture 23, slide 23).
  6. What values are written to a bus's data, address, and control lines?
  7. What is the difference between synchronous and asynchronous buses? Between parallel and serial buses?
  8. Given a bus design, be able to calculate the bus bandwidth (Lecture 24, slide 14).
  9. What does bus mastering mean?
  10. When an interrupt arrives, how does the processor know what the PC should be set (Lecture 14, slide 17 and Lecture 25, slide 6).
  11. What does it mean to mask an interrupt? Why should interrupts be masked?
  12. What is the advantage of message signaled interrupts?

Parallel Processing

  1. What is the cache coherence problem? Why does a processor snoop the memory bus? (Lecture 20, slide 21).
  2. Give an example of SISD, SIMD, MISD, and MIMD.
  3. What is the advantage of centralized shared memory? Of distributed memory?
  4. Define the terms issue slot and issue packet.
  5. What are the advantages/disadvantage of single pipeline, VLIW, and superscalar pipelines?
  6. Given a processor design and instruction stream, be able to calculate how many cycles are needed to execute all of the instructions (Lecture 26, slide 12).
  7. What is the difference between fine-grained superthreading, course-grained superthreading, and simultaneous multithreading?