Lecture & Homework Schedule

Standard disclaimer: dates are subject to change.

Date Lecture Homework Reading
Tue 01/28 1. Introduction HW1 assigned Sections 1.1 - 1.5
Thu 01/30 2. Instruction Semantics Sections 2.1 - 2.3, 2.5 - 2.8
Tue 02/04 3. Runtime Environment Sections 2.8, 2.10 - 2.13
Thu 02/06 4. Peformance Metrics Sections 1.6, 1.9 - 1.10
Tue 02/11 5. Boolean Logic HW1 due at 11:59:59 PM, HW2 assigned Sections A.2 - A.3
Thu 02/13 6. Integer Representations Sections 2.4 - 2.6, 2.9, 3.2
Tue 02/18 7. Arithmetic Logic Unit Sections A.5 - A.6
Thu 02/20 8. Multiplication Sections 3.3
Tue 02/25 9. Division HW2 due at 11:59:59 PM; Proj 1 assigned Sections 3.4
Thu 02/27 Midterm 1
Tue 03/03 10. Floating Point Sections 3.5
Thu 03/05 11. Datapaths Sections A.7 - A.8, 4.1 - 4.3
Tue 03/10 12. Single-Cycle Control Unit Sections 4.4
Thu 03/12 Class Cancelled
Tue 03/17 Spring Break
Thu 03/19 Spring Break
Tue 03/24 13. Multi-Cycle Control Unit Proj1 due at 11:59:59 PM; HW3 assigned Sections 4.5
Thu 03/26 14. Microprogramming and Exceptions Sections 4.9
Tue 03/31 15. Pipelining Sections 4.5
Thu 04/02 16. Pipeline Controls Sections 4.6
Tue 04/07 17. Pipeline Hazards HW3 due at 11:59:59 PM; HW4 assigned Sections 4.7 - 4.9
Thu 04/09 Midterm 2
Tue 04/14 18. Memory Systems Sections 5.1 - 5.3, A.9
Thu 04/16 19. Cache Performance Sections 5.3 - 5.4
Tue 04/21 20. Multi-Cache Designs Sections 5.8 - 5.10
Thu 04/23 21. Virtual Memory HW4 due at 11:59:59 PM; Proj2 assigned Sections 5.7
Tue 04/28 22. Address Spaces AMD64 Architecture Manual, sections 5.3 - 5.4; A Guide to Using Direct Memory Access
Thu 04/30 23. I/O Performance Sections 5.5
Tue 05/05 24. Bus Interconnects Everything You Need to Know About the PCI Express, How PCI express devices talk
Thu 05/07 25. Interrupt Handling and Multi-Data Processing Sections 6.3
Tue 05/12 26. Parallel Processing Sections 4.10, 6.4
Thu 05/14 Final Exam (6:00pm – 8:00pm)
Sun 05/17 Proj2 due at 11:59:59 PM