UMBC CMSC 313, Computer Organization & Assembly Language, Fall 2002, Section 0101

Finite State Machines

Thursday 11/14, 2002

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Assigned Reading in Murdocca & Heuring:  A.12-A.15

Assigned Reading in Neveln:   

Assigned:  DigSim2

Due:  HW4

Topics Covered:

• Recap SR latches, D latches, master-slave D flip-flops.
• Examined a race condition that might occur while putting together a master-slave D flip-flop.
• Examined a negative edge triggered D flip-flop.
• Introduction to finite state machines.
• Constructed a Mod-4 counter.
• Discussed DigSim Exercise 2. Noted that D flip-flops in DigSim are positive edge triggered.

Circuits in DigSim:

Following these links will launch the DigSim Java applet and load the circuit described.

• An SR flip-flop (latch)
• A clocked SR flip-flop (latch)
• A D flip-flop (latch)
• A master-slave D flip-flop
• A master-slave D flip-flop with a race condition problem
• A negative edge triggered D flip-flop
• A Mod-4 Counter