UMBC CMSC 313, Computer Organization & Assembly Language, Fall 2002, Section 0101

Flip Flops

Tuesday 11/12, 2002

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Assigned Reading in Murdocca & Heuring:  A.11

Assigned Reading in Neveln:   

Assigned:   

Due:   

Topics Covered:

• Introduction to sequential logic.
• A model of a finite state machine with flip-flops acting acting as memory elements.
• The basic idea of a latch illustrated with a relay and with two inverters.
• An SR flip-flop (latch) constructed from two NOR gates and from two NAND gates.
• Using a clock to solve the problem of glitches and hazards.
• Clocked SR flip-flops and clocked D flip-flops.
• Some timing issues solved with a master-slave D flip-flop.
• Clocked J-K flip-flops and the endless toggle problem.
• Master-Slave J-K flip-flops.
• Negative-edge triggered D flip-flop.
• On flip-flops and latches: the terminology for flip-flops and latches have not been standardized. What one textbook calls a latch another may call a flip-flop. Our textbook (M&H) calls everything a flip-flop. Here's what some other textbooks use. Both latches and flip-flops refer to sequential circuit constructs that "remember" or "record" a certain input signal at some point in time.
  • A latch is often used for circuits where the output changes right after the input changes, without reference to any clocking event. What our text calls an SR flip-flop is often called an S-R latch in other textbooks.
  • A level-sensitive latch is a latch that operates only when the clock is high or only when the clock is low. What our text calls a clocked SR flip-flop is called a level-sensitive SR latch in some other texts.
  • The term flip-flop is often reserved for circuits that record the input only during certain clocking events. The expectation is that the output does not also change during this clocking event. The master-slave flip-flops described in our text-book certainly fits this category.
  • An edge-triggered flip-flop is a flip-flop that only records the input during a low-to-high (positive edge triggered) or a high-to-low (negative edge triggered) transition of the clock. The input signal must be stable for a duration (the setup time) prior to the clock transition and must remain stable for a duration called the hold time. There is some disagreement on whether a master-slave flip-flop is an edge-triggered flip-flop. My interpretation is that it is not. Our textbook uses the symbol for an edge-triggered flip-flop for the master-slave D flip-flop. Another textbook does the same thing, but does mention that some people do not consider master-slave flip-flops to be edge-triggered. Still another textbook puts master-slave flip-flops in a category all by itself. (One problem here is that one might reasonably argue that a master-slave D flip-flop is negative edge triggered, but a master-slave JK flip-flop really isn't edge triggered.)

Circuits in DigSim:

Following these links will launch the DigSim Java applet and load the circuit described.

• An SR flip-flop
• A clocked SR flip-flop
• D flip-flop
• Master-Slave D flip-flop
• JK flip-flop
• A master-slave JK flip-flop
• A negative edge triggered D flip-flop