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CS411 Details of homework assignments HW1..HW6 and Midterm
The most important item on all homework is YOUR NAME!
AND last 4 digits of SS#. No name or SS#, no credit.
Staple or clip pages together.
Homework must be submitted when due. You loose 10%, one grade,
the first day homework is late. Then 10% each week thereafter.
Max 50% off. A zero really hurts your average!
Paper or EMail to squire@umbc.edu ONLY PLAIN TEXT.
I can NOT accept OCTET/STREAM. .doc .gif .jpg .rtf ...
If I can not read or understand your homework, you do
not get credit. Type or print if your handwriting is bad.
Homework is always due on a scheduled class day within 15 minutes
after the start of the class. If class is canceled then homework
is due the next time the class meets. EMailed homework has until
midnight the day of the last sections due date.
EMail only plain text! No word processor formats.
You may use a word processor or other software tools and
print the results and turn in paper.
Put CS411 and HW number in subject line.
Put last four digits of SS# on homework (in attachments).
Email HW 1,2,3, 5, 7,8,9,10,11,12 BUT submit HW4,6 part 1-3
The "submit" facility only works on the "irix.gl" and "linux.gl" machines.
The student commands are:
submit cs411 HW4 file puts your "file" into cs411 HW4
submitrm cs411 HW4 file removes your "file" from cs411 HW4
submitls cs411 HW4 lists your files in cs411 HW4
Note: For this semester the 'HW4' can be HW4, HW6, part1, part2 or part3.
a) you must have your userid registered for "submit"
send mail from a gl machine to squire if your submit fails
b) you have to be logged onto a gl machine, kermit or telnet are OK
c) everything is case sensitive, sorry about the uppercase HW.
Do your own homework!
You can discuss homework with other class members but DO NOT COPY!
All parties involved in copying get zero on that assignment.
Homework 1
Homework 2
Homework 3
Homework 4
Homework 5
Homework 6
Midterm Exam
Other Links
Book Page 45, Exercises 1.1 through 1.26.
The answer is just two columns. The first column is the numbers
1 through 26, the second column is the answer letter from the set {a-z}
You do not have to copy the questions, but show the
computation and clearly indicate the answers.
Be sure to label the answers with the Exercise number.
Book Page 93, Exercises 2.18, 2.19, 2.20 with the following changes:
Table a. A 2 30%
B 2 40%
C 3 20%
D 4 10%
Table b. A 2 30%
B 3 40%
C 3 20%
D 5 10%
"How much faster" is a dimensionless ration faster/slower,
this is called "speed up" always greater than 1.0
Book Page 101, Exercise 2.41 with the following changes:
"half the 10 seconds" becomes "two thirds the 10 seconds"
Book Page 101, Exercise 2.44
Be sure to work all problems and all subparts of each problem.
Zero points will be given if changes are not used.
Using the program matmul2.c from here or Downloadable source:
On a GL SGI machine, MIPS architecture only, irix.gl.umbc.edu
The Textbook and Project require you know a few SGI instructions
and their formats.
Part 1. Compare the assembly language printed by two compilers.
Part 2. Compare the assembly language printed by the compiler vs
the instructions in memory at execution time.
Note: The answers are not unique. It depends on which
compiler is used, which specific machine is used and
which options are used.
This assignment must be run on a GL SGI machine using:
c89 -g3 -O3 SGI compiler
gcc -g3 -O3 gnu compiler (much different on MIPS architecture)
^_____ letter upper case oh, NOT zero !
--------------------------------------------------------------------
Part 1
for getting assembly language source code to a file matmul2.s
gcc -g3 -O3 -S matmul2.c (creates matmul2.s)
mv matmul2.s matmul2gcc.s (save, next clobbers.)
c89 -g3 -O3 -S matmul2.c (creates matmul2.s differently)
mv matmul2.s matmul2sgi.s
Now, look in the files matmul2gcc.s and matmul2sgi.s
Ignore all lines where the first character is a dot "."
a) How may mul.d instructions in matmul2gcc.s ?
b) About how many mul.d instructions in matmul2sgi.s ?
------------------------------------------------------------------
Part 2
When running with redirection, ">", first test without redirection
to be sure you can type the correct input and it works. Then
type carefully or use a script to make the redirected run.
Extra "enter" keys may be needed at various places.
Ignore warning messages from debugger.
Remember memory addresses are in bytes, instructions take 4 bytes.
(Even in the 64 bit machine!)
In hex.out use an address to relate to memory to find the same word.
In the following sequences of commands, blank lines are typed as "enter"
Ignore information and error messages. Type very carefully!
c89 -g3 -O3 matmul2.c # need debug, -g3, for "stop main" to work
dbx -d a.out > hex.out
stop main
rerun
list 1,26
(#1)/100X
(#1)/100i
q
The file hex.out has the source listing with line numbers,
the hex address and hex instructions as loaded in memory and
the deassembly with hex address and decoded instruction.
The instruction field format is on page 117 of textbook, also 121, 131 or
appendix A-73 area.
mul.d is the MIPS=SGI double precision floating point multiply, "R" format.
Watch out for where the register values are placed.
(R2000 instructions differ from IRIX.GL.UMBC.EDU that are R??000.)
Most of the instruction in the loop are "housekeeping", there are various
instructions for loading and storing data, l.d and s.d are just one pair.
a) Do the instructions have the same names in matmul2sgi.s and hex.out ?
b) Find a mul.d instruction in hex.out [use this for c) and d) ]
Write an assembly language line, note the machine address.
c) From the machine address, write the mul.d as hexadecimal and
d) Write the mul.d as six integers for the fields 6,5,5,5,5,6 bits
"submit" a single file named add32.vhdl that is a fast carry 32 bit adder.
You will use this file in HW6 and project, don't trash it.
It is not important what the signal names are inside add32.vhdl,
but keep the same interface, the entity declaration.
entity add32 is
port(a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
cin : in std_logic;
sum : out std_logic_vector(31 downto 0);
cout : out std_logic);
end entity add32;
Build a four bit fast adder component or download and include
add4.vhdl
cp ~squire/www/add4.vhdl . # on cadence1.cs.umbc.edu
cp add4.vhdl add32.vhdl
You need a 32 bit adder, so use eight add4 components in
an add32 component, cin goes into bottom
stage, the carry out of each stage goes into the bottom of the next stage,
the carry out from the last stage gets the signal name cout.
Use unique signal names or unique subscripts. All connections with
the same name are tied together and have the same value.
For testing your add32 component download tadd32.vhdl and tadd32.run
cp ~squire/www/tadd32.vhdl .
cp ~squire/www/tadd32.run .
cp ~squire/www/tadd32.chk .
Use these commands to set up VHDL, then compile and simulate:
On cadence1.cs.umbc.edu (use ssh to get there using your CS account.)
First: You must have an account on a CSEE machine because the Cadence
software is licensed to this specific machine.
This is in addition to your gl account but may be the same
user id. Use ssh cadence1.cs.umbc.edu
or ssh cadence2.cs.umbc.edu
Next: Follow instructions exactly or you figure out a variation.
be in your home directory on cadence1 or 2 and then type commands:
cp /home/faculty4/squire/www/cs411.tar .
tar -xvf cs411.tar
cd vhdl
tcsh
source vhdl_cshrc
make
more ctest1.out
make clean # saves a lot of disk quota
Then do your own thing with Makefile for HW4, then HW6 ...
You can most easily use this directory for HW4, HW6, and
the five parts of the project.
(Modify Makefile, change ctest1 to tadd32 and fix as shown below.)
ncvhdl -v93 add32.vhdl
ncvhdl -v93 tadd32.vhdl
ncelab -v93 tadd32:circuits
ncsim -batch -logfile tadd32.out -input tadd32.run tadd32
Check to file tadd32.out to be sure your adder worked.
The answers are in tadd32.chk
You can check your output with the command
diff -w tadd32.out tadd32.chk
On cadence1 type klog give your GL password, then
cp add32.vhdl /afs/umbc.edu/users/u/s/userid/home # your u/s/userid
Submit ONE file add32.vhdl that has the entity add32 in it.
ssh irix.gl.umbc.edu
submit cs411 HW4 add32.vhdl
Your circuits must run. Incorrect results loose points.
You must include a few comments so anyone reading your circuits can
understand them.
Follow the links below to Project and Download for more information.
See the writeups on VHDL and sample circuits.
The building blocks may become part of your final project.
1. Write two VHDL statements that implement the truth table below
Just use "and" "or" and "not" with parenthesis.
the answer starts x <=
y <=
a b c | x y
------+----
0 0 0 | 0 0
0 0 1 | 0 0
0 1 0 | 1 0
0 1 1 | 1 1
1 0 0 | 0 0
1 0 1 | 1 0
1 1 0 | 0 1
1 1 1 | 0 0
2. Write the VHDL statement that implements the logic diagram
+----+
a --|XOR |____
b --| | |
+----+ | +----+
--| OR |
+----+ | |
c --|AND |_____| |__
d --| | | | |
+----+ | | |
--| | |
+----+ | | | |
e --|NOT |---| +----+ | +----+
+----+ |--|OR |
| |-- g
f ------------------------| |
+----+
3. Draw the logic diagram that represents the VHDL statement
g <= ((not a or b) xor (c and not d and not e)) or (not e and f);
4. textbook, Page 330, Problem 4.49 with the additional instructions:
Use A, B, E and F all as four ones. e.g. A <= "1111" etc.
The answer is a six bit result S.
5. textbook, page 331, Problem 4.50
Watch out, the problem states 2T, not 1T per block.
Be sure to count the longest path.
Code a circuit using one 32 bit adder that performs a serial multiply
followed by a serial divide. Use 32 bit numbers with the sign bit set
to zero. You do not have to correct the remainder after division.
You may use one or more counters, as many multiplexers
and assorted gates, signals, clocks as you need. But, only one
32 bit adder. Use your HW4 adder.
You may use the sample VHDL code from the download directory, printed
copy handed out and discussed in class, for the multiplier
mul_ser.vhdl and for the divider div_ser.vhdl
Partial schematics for multiplier mul_ser.gif
and for the divider div_ser.gif
Basically, copy mul_ser.vhdl to mul_div_ser.vhdl, replace string
"mul_ser" with "mul_div_ser",
add multiplexors to input to "hi", "lo", "add32",
add or enlarge counter(s), put in logic to get "mulenb" to be '1'
when doing multiply and "divenb" to be '1' when doing divide. Use
the enable signals to control the multiplexors.
The partial schematic for the multiplexors that are needed is
Be sure to put the modified mulenb <= ... and divenb <= ...
into mul_div_ser.vhdl replacing the existing lines.
Carefully copy lines from div_ser.vhdl that are needed.
These include "signal ..." lines not already in mul_ser.vhdl.
These include "xxx <= ..." lines where xxx <= is not already in mul_ser.vhdl
Change "hi<=" and "lo<=" from mul_ser.vhdl to "mulhi<=" and "mullo<="
removing the "mulclk'event and mulclk='1'"
Change "hi<=" and "lo<=" from div_ser.vhdl to "divhi<=" and "divlo<="
removing the "divclk'event and divclk='1'"
This exercise is intended to show how a more "expensive" circuit
such as a fast adder, can be shared by several operations.
You must use only one adder, one "hi" register, one "lo" register.
It is generally considered that multiplexors are not expensive.
Set up your circuit to perform the multiplication of 63 times 84 with
the resulting 64 bit product in the "hi" "lo" registers.
63 is written x"0000003F" in VHDL, 84 is x"00000054". Multiply should
take 32 clocks. Then you circuit divides the "hi" "lo" registers
by 15 with the quotient in the "lo" register and the remainder in
the "hi" register. This should take an additional 32 clocks.
Notice that if you use one register for "md" then you need to
change the value from x"0000003F" to x"0000000F" when
cntr="0100010". The alternative is to use a "multiplicand" and
a "divisor" register in place of the "md" register.
Special! clock "sub_add" when divclk'event and divclk='1'
otherwise it can change its initial value during multiply.
DO NOT implement the Booth multiply, do use the non-restoring
divide algorithm.
Have everything needed for the simulation in one file named
mul_div_ser.vhdl (This includes counter(s) and test driver
circuit with printout.) Your HW4 add32.vhdl does not have to
be included, it can be compiled by your Makefile.
Produce labeled print out, using "write" statements for at least
the "hi" "lo" and clock counter, "cntr"
Check that at the end of the multiply, "hi" and "lo" have
the value 63 times 85. (The counter may read 31 or zero or
32 if you used a 6 bit counter.)
Check that at the end of divide, "hi" has the remainder of
(63 * 84) / 15 and "lo" has the quotient of (63 * 84) / 15.
The counter value is not important, but stop the simulation
when the result is correct in "hi" and "lo" or soon after that.
When the check is OK, use klog and cp to get your file to GL, then
submit cs411 HW6 mul_div_ser.vhdl
Note: You loose one point if file name is not "mul_div_ser.vhdl"
You loose one point if entity name is not "mul_div_ser"
You loose one point if architecture name is not "schematic"
Why? Because we run a script to grade this homework.
Use your add32 component from HW4. Ask instructor for a working
add32.vhdl if your HW4 did not seem to work.
Other files may be most conveniently obtained:
cp /web/www/help/VHDL/samples/mul_ser.vhdl .
cp /web/www/help/VHDL/samples/div_ser.vhdl .
cp /web/www/help/VHDL/samples/mul_ser.run . # double time to 700 ns and
# rename to mul_div_ser.run
You can modify the "Makefile" changing the name to mul_div_ser
from whatever is in there, or add a new group to the "Makefile"
e.g.
all: mul_div_ser.out
mul_div_ser.out: mul_div_ser.vhdl
ncvhdl -v93 add32.vhdl # from your HW4
ncvhdl -v93 mul_div_ser.vhdl
ncelab -v93 mul_div_ser:schematic
ncsim -batch -logfile mul_div_ser.out \
-input mul_div_ser.run mul_div_ser
My output is mul_div_ser.out
or mul_div_ser.chk
Ask if your "hi" and "lo" is different. There may be multiple solutions.
Add to the print process whatever you need to check out your circuit.
leave the printout of "hi" and "lo". Theses are the only results that
are checked. The last four columns of my printout are:
mulenb divenb quo sub_add .
Closed book. Multiple choice questions based on reading assignments,
lectures, handouts and homework.
Exam covers book: 1.1-1.6 common sense questions, not dates or people
2.1-2.6
page 118, 146 and 148 instruction formats
4.1-4.8
5.1-5.3 just instructions covered in class
(nop, j, beq, add, sub, sll, srl, cmpl, lw, sw)
Exam covers homework: HW1-HW5
Be sure to go over handouts,
no questions on current events handouts
Last updated 3/12/03