Naghmeh Karimi

Book Chapters

4. N. Karimi, "Security and Device Aging," In Encyclopedia of Cryptography, Security and Privacy, 3rd Edition, Springer, USA, 2019 [link]

3. N. Karimi and Z. Navabi, "VHDL-AMS Hardware Description Language," In The VLSI Handbook, 2nd Edition, Chapter 91, Section XIII, CRC Press, USA, 2006 [link]

2. N. Karimi and Z. Navabi, "ASIC and Custom IC Cell Information Representation," In The VLSI Handbook, 2nd Edition, Chapter 93, Section XIII, CRC Press, USA, 2006 [link]

1. N. Karimi and Z. Navabi, "Timing Description Languages," In The VLSI Handbook, 2nd Edition, Chapter 95, Section XIII, CRC Press, USA [link]

Journal Articles

27. M. Ebrahimabadi, S. S. Mehjabin, R. Viera, S. Guilley, J.-L. Danger, J.-M. Dutertre, and N. Karimi, “DELFINES: Detecting Laser Fault Injection Attacks via Digital Sensors,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Accepted for Publication, 2023

26. M. T. H. Anik, J.-L. Danger, O. Diankha , M. Ebrahimabadi, C. Frisch, S. Guilty, N Karimi, M. Pehl, and S. Takarabt, “Testing and Reliability Enhancement of Security Primitives: Methodology and Experimental Validation,“ Elsevier Journal of Microelectronics Reliability, vol. 147, 2023

25. S. S. Mehjabin, A. Tekeoglu, M. Younis, M. Ebrahimabadi, R. Chandran, T. Sookoor, and N. Karimi, “A Networked System Dependability Validation Framework using Physical and Virtual Nodes,” IEEE Access, Accepted for Publication, 2023

24. T. Kroeger, W. Cheng, S. Guilley, J.-L. Danger, and N. Karimi, “Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs,” Springer Journal of Electronic Testing (JETTA), vol. 38, no. 3, pp. 261–277, 2022 [PDF]

23. T. Kroeger, W. Cheng, S. Guilley, J.-L. Danger, and N. Karimi, “Assessment and Mitigation of Power Side-Channel based Cross-PUF Attacks on Arbiter-PUFs and their Derivatives,” IEEE Trans. on Very Large Scale Integration Systems (TVLSI), vol. 30, no. 2, pp. 187-200, 2022 [PDF]

22. M. T. H. Anik*, M. Ebrahimabadi*, J.-L. Danger, S. Guilley, and N. Karimi, “Reducing Aging Impacts in Digital Sensors via Run-time Calibration, ” Springer Journal of Electronic Testing (JETTA), vol. 37, no. 5-6, pp. 653-673, 2022 *equal contribution [PDF]

21. W. Lalouani, M. Younis, M. Ebrahimabadi, and N. Karimi, “Countering Modeling Attacks in PUF-based IoT Security Solutions,” , ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 18, issue 3, no. 46, pp 1–28, 2022 [PDF]

20. M. Ebrahimabadi, M. Younis, and N. Karimi, “A PUF-Based Modeling-Attack Resilient Authentication,” IEEE Internet of Things (IoT) Journal, vol. 9, no. 5, pp. 3684-3703, 2022 [PDF]

19. F. Niknia, Danger, J.-L. Danger, S. Guilley, and N. Karimi, "Aging Effects on Template Attacks Launched on Dual-Rail Protected Chips," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 5, pp. 1276-1289, 2022 [PDF]

18. B. Fadaeinia, M. T. H. Anik, N. Karimi, and A. Moradi, “Masked SABL: a Long Lasting Side-Channel Protection Design Methodology,” IEEE Access, vol. 9, pp. 90455-90464, 2021 [PDF]

17. A. Vakil, A. Mirzaei, H. Homayoun, N. Karimi, A. Sasan, “AVATAR: NN-Assisted Variation Aware Timing Analysis & Reporting for Hardware Trojan Detection,” IEEE Access, vol. 9, pp. 92881 - 92900, 2021 [PDF]

16. N. Karimi, K. Basu, C.-H. Chang, and J. M. Fung, “Hardware Security in Emerging Technologies: Vulnerabilities, Attacks, and Solutions,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 11, no. 2, pp. 223-227, 2021 [PDF]

15. W. Liu, C.-H. Chang, X. Wang, C. Liu, J. Fung, M. Ebrahimabadi, N. Karimi, X. Meng, and K. Basu, “Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 11, no. 2, pp. 228 - 251, 2021 [PDF]

14. M. T. H. Anik, J.-L. Danger, S. Guilley, and N. Karimi, "Detecting Failures and Attacks via Digital Sensors," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 40, no. 1, pp. 1315 - 1326, 2021 [PDF]

13. N. Karimi, T. Moos, and A. Moradi, "Exploring the Effect of Device Aging on Static Power Analysis Attacks&," IACR Trans. on Cryptographic Hardware and Embedded Systems (CHES), pp. 233-256, 2019 [PDF]

12. J. Shey, N. Karimi, R. Robucci, and C. Patel,"Implementation-Based Design Fingerprinting for Robust IC Fraud Detection," Journal of Hardware and Systems security, vol. 3, no. 4, pp.426-439, 2019 [PDF]

11. K. Huang, X. Zhang, and N. Karimi, "Real-Time Prediction for IC Aging based on Machine Learning," IEEE Trans. on Instrumentation and Measurement (TIM), vol. 68, no. 12, PP.4756-4764, 2019 [PDF]

10. N. Karimi, J. Danger, and S. Guilley,"Impact of Aging on the Reliability of Delay PUFs," Springer Journal of Electronic Testing: Theory and Applications (JETTA), vol. 34, no. 5, pp.571-586, 2018 [PDF]

9. N. Karimi , A. Kanuparthi, X. Wang, O. Sinanoglu, and R. Karri, "MAGIC: Malicious Aging in Circuits/Cores," ACM Trans. on Architecture and Code Optimization (TACO), vol. 12, no. 1, pp. 5.1-5.25, 2015 [PDF]

8. S. Kannan, N. Karimi , R. Karri, and O. Sinanoglu, "Modeling, detection, and diagnosis of faults in multi-level memristor memories," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.34, no.5, pp. 822-834, 2015 [PDF]

7. S. Kannan, N. Karimi , O. Sinanoglu, and R. Karri, "Security vulnerability of emerging non-volatile main memories and countermeasures," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 1, pp. 2-15, 2015 [PDF]

6. A. DeTrano, N. Karimi , R. Karri, X. Guo, C. Carlet, and S. Guilley, "Exploiting small leakages in masks to turn a second-order attack into a first-order attack and improved rotating substitution box masking with linear code cosets," The Scientific World Journal, vol. 2015, pp. 1-10, 2015 [PDF]

5. N. Karimi and K. Chakrabarty, "Detection, diagnosis and recovery from clock-domain crossing failures in multi-clock SoCs," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 9, pp. 1395-1408, 2013 [PDF]

4. N. Karimi , M. Maniatakos, C. Tirumurti, and Y. Makris, "On the impact of performance faults in modern microprocessors," Journal of Electronic Testing : Theory and Applications (JETTA), vol. 29, no. 3, pp. 351-366, 2013 [PDF]

3. N. Karimi , M. Maniatakos, A. Jas, C. Tirumurti, and Y. Makris, "Workload-cognizant concurrent error detection in the scheduler of a modern microprocessor," IEEE Trans. on Computers (TCOMP), vol. 60, no. 9, pp. 1274-1287, 2011 [PDF]

2. M. Maniatakos, N. Karimi , C. Tirumurti, A. Jas, and Y. Makris, "Instruction-level impact analysis of low-level faults in a modern microprocessor controller," IEEE Trans. on Computers (TCOMP), vol. 60, no. 9, pp. 1260-1273, 2011 [PDF]

1. N. Karimi , A. Alaghi, M. Sedghi, and Z. Navabi, "Online network-on-chip switch fault detection and diagnosis using functional switch faults," Journal of Universal Computer Science (JUCS), vol. 14, no. 22, pp. 3716-3736, 2008 [PDF]

Conference Papers

63. M. Ebrahimabadi, J. Bahrami, M. Younis, and N. Karimi, "Digital Twin Integrity Protection in Distributed Control Systems," Proc. IEEE Consumer Communications \& Networking Conference (CCNC), Accepted for Publication, 2024

62. J. Bahrami, J.L- Danger, M. Ebrahimabadi, S. Guilley, and N. Karimi, "Challenges in Generating True Random Numbers Considering the Variety of Corners, Aging, and Intentional Attacks," Proc. Int'l Conf. on IC Design and Technology (ICICDT), 2023

61. S. Kai, T. Kondo, N. Karimi, K. Mersinas, M. Sel, R. Yus, and S. Tezuka, "International Mutual Recognition: A Description of Trust Services in US, UK, EU and JP and the Testbed Hakoniwa," Proc. Int'l Conf. on Security and Cryptography (SECRYPT), 2023, pp. 764-771

60. M. L. Sel, H. I. Reefat, N. Karimi, and K. Mersinas, "Evaluation of Entity Trustworthiness Based on Public and Private Data," IFIP Int'l Conf. on Trust Management (IFIPTM), 2023

59. S. Takarabt, J. Bahrami, M. Ebrahimabadi, S. Guilley, and N. Karimi, "Security Order of Gate-Level Masking Schemes," Proc. Hardware Oriented Security and Trust (HOST), 2023 [PDF]

58. J. Bahrami, M. Ebrahimabadi, J.L- Danger, S. Guilley, and N. Karimi, "Security Verification & Testing for SR-Latch TRNGs," Proc. VLSI Test Symp. (VTS), 2023 [PDF]

57. M. T. H. Anik, H. I. Reefat, J.-L. Danger, S. Guilley, and N. Karimi, "Aging-Induced Failure Prognosis via Digital Sensors," Proc. ACM Great Lakes Symp. on VLSI (GLSVLSI), 2023 [PDF]

56. M. Ebrahimabadi, M. Younis, W. Lalouani, A. Alshaeri, and N. Karimi, "SWeeT: Security Protocol for Wearables Embedded Devices' Data Transmission,'' Proc. IEEE Int’l Conf. on E-health Networking, Application and Services (HealthCom), 2022, pp. 135.141 [PDF]

55. W. Lalouani, M. Younis, M. Ebrahimabadi, and N. Karimi, "Collusion-resistant PUF-based Distributed Device Authentication Protocol for Internet of Things," Proc. IEEE Global Communications Conference: IoT and Sensor Networks (GLOBECOM), 2022, pp. 4328-4333 [PDF]

54. J. Bahrami, M. Ebrahimabadi, S. Takarabt, J.-L. Danger, S. Guilley, and N. Karimi, "On the Practicality of Relying on Simulations in Different Abstraction Levels for Pre-Silicon Side-Channel Analysis," Proc. Int'l Conf. on Security and Cryptography (SECRYPT), 2022 [PDF]

53. M. Sadi, Y. He, Y. Li, M. Alam, S. Kundu, S. Ghosh, J. Bahrami, and N. Karimi, "On the Reliability of Conventional and Quantum Neural Network Hardware," Proc. IEEE VLSI Test Symp. (VTS), 2022 [PDF]

52. M. Ebrahimabadi, S. S. Mehjabin, R. Viera, S. Guilley, J.-L. Danger, J.-M. Dutertre, and N. Karimi, “Detecting Laser Fault Injection Attacks via Time-to-Digital Converter Sensors,” Proc. Hardware-Oriented Security and Trust Symp. (HOST), 2022, pp. 97-100 [PDF]

51. M. Ebrahimabadi, B. Fadaeinia, A. Moradi, and N. Karimi, “Does Aging Matter? The Curious Case of Fault Sensitivity Analysis,” Proc. IEEE Int'l Symp. on Quality Electronic Design (ISQED), 2022, pp. 84-89 [PDF]

50. M. Ebrahimabadi, M. Younis, W. Lalouani, and N. Karimi, “An Attack Resilient PUF-based Authentication Mechanism for Distributed Systems,” Proc. IEEE Int’l Conf. on VLSI Design (VLSID), 2022, pp. 108-113 [PDF]

49. J. Bahrami, M. Ebrahimabadi, J.-L. Danger, S. Guilley, and N. Karimi, “Leakage Power Analysis in Different S-Box Masking Protection Schemes,” Proc. IEEE Design Automation & Test in Europe (DATE), 2022, pp. 1263-1268 [PDF]

48. W. Lalouani, M. Younis, M. Ebrahimabadi, and N. Karimi, “Robust and Efficient Data Security Solution for Pervasive Data Sharing in IoT,” Proc. IEEE Consumer Communications & Networking Conference (CCNC), 2022, pp. 775-781 [PDF]

47. T. Kroeger, W. Cheng, S. Guilley, J.-L. Danger, and N. Karimi, “Making Obfuscated PUFs Secure Against Power Side-Channel Based Modeling Attacks,” Proc. IEEE Design Automation & Test in Europe Conf. (DATE), 2021, pp. 454-459 [PDF]

46. M. T. H. Anik, B. Fadaeinia, A. Moradi, and N. Karimi, “On the Impact of Aging on Power Analysis Attacks Targeting Power-Equalized Cryptographic Circuits,” Proc. IEEE Asia and South Pacific Design Automation Conference Conf. (ASP-DAC), pp. 414-420, 2021 [PDF]

45. A. Vakil, F. Niknia, A. Mirzaeian, A. Sasan, and N. Karimi, “Learning Assisted Side Channel Delay Test for Detection of Recycled ICs,” Proc. IEEE Asia and South Pacific Design Automation Conference Conf. (ASP-DAC), 2021, pp. 455-462 [PDF]

44.M. T. H. Anik, J.-L. Danger, O. Diankha , M. Ebrahimabadi, C. Frisch, S. Guilty, N Karimi, M. Pehl, and S. Takarabt, "Testing and Reliability Enhancement of Security Primitives," Proc. IEEE Int'l Symp. on Defect and Fault Tolerance of VLSI Systems (DFTS), 2021, pp. 1-8 [PDF]

43. M. Ebrahimabadi, M. Younis, W. Lalouani, and N. Karimi, “A Novel Modeling-Attack Resilient Arbiter-PUF Design,” IEEE Int’l Conf. on VLSI Design (VLSID), 2021, pp. 123-128 [PDF]

42. M. Ebrahimabadi, M. Younis, N. Karimi, "Hardware Assisted Smart Grid Authentication," Proc. IEEE Int'l Conf. on Communications (ICC), 2021 [PDF]

41. M. Ebrahimabadi, W. Lalouani, M. Younis, N. Karimi, “Countering PUF Modeling Attacks through Adversarial Machine Learning,” Proc. IEEE Computer Society Annual Symp. on VLSI (ISVLSI), 2021 [PDF]

40. T. Kroeger, W. Cheng, S. Guilley, J.-L. Danger, and N. Karimi, “Enhancing the Resiliency of Multi-Bit Parallel Arbiter-PUF and its Derivatives against Power Attacks,” Proc. Int’l Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE), 2021 [PDF]

39. K. Huang, M. T. H. Anik, X. Zhang, and N. Karimi, “Real-Time IC Aging Prediction via On-Chip Sensors,” Proc. IEEE Computer Society Annual Symp. on VLSI (ISVLSI), 2021 [PDF]

38. M. Ebrahimabadi, M. T. H. Anik, J.-L. Danger, S. Guilley, and N. Karimi, “Using Digital Sensors to Leverage Chips’ Security,” Proc. IEEE Int’l Conf. on Physical Assurance and Inspection of Electronics (PAINE) 2020 [PDF]

37. T. Kroeger, W. Cheng, S. Guilley, J.-L. Danger, and N. Karimi , "Cross-PUF Attacks on Arbiter-PUFs through Their Power Side-Channel," Proc. IEEE Int'l Test Conf. (ITC), 2020, pp. 1-5 [PDF]

36. M. T. H. Anik, M. Ebrahimabadi, H. Pirsiavash, J.-L. Danger, S. Guilley, and N. Karimi , "On-Chip Voltage and Temperature Digital Sensor for Security, Reliability, and Portability," Proc. IEEE Int'l. Conf. on Computer Design (ICCD), 2020, pp. 1-4 [PDF]

35. T. Kroeger, W. Cheng, S. Guilley, J.-L. Danger, and N. Karimi , "Effect of Aging on PUF Modeling Attacks Based on Power Side-Channel Observations," Proc. IEEE Design Automation & Test in Europe Conf. (DATE), 2020, pp. 454-459 [PDF]

34. M. T. H. Anik, S. Guilley, J.-L. Danger, and N. Karimi , "On the Effect of Aging on Digital Sensors," Proc. IEEE Int'l Conf. on VLSI Design (VLSID), 2020, pp. 189-194 [PDF]

33. A. Alipour, V. Beroulle, B. Cambou, J.-L. Danger, G. Di Natale, D. Hely, S. Guilley, and N. Karimi , "PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community," Proc. IEEE European Test Symp. (ETS), 2020, pp. 1-10 [PDF]

32. M. T. H. Anik, R. Saini, J.-L. Danger, S. Guilley, and N. Karimi , "Failure and Attack Detection by Digital Sensors," Proc. IEEE European Test Symp. (ETS), 2020, pp. 1-2 [PDF]

31. S. Roshanisefat, H. M. Kamali, K. Z. Azar, S. M. P. Dinakarrao, N. Karimi , H. Homayoun,and A. Sasan, "DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain," Proc. IEEE VLSI Test Symp.(VTS), 2020, pp.1-6 [PDF]

30. A. Vakil, F. Behnia, A. Mirzaeian, H. Homayoun, N. Karimi , and A. Sasan, "LASCA: LearningAssisted Side Channel Delay Analysis for Hardware Trojan Detection,", Proc. IEEE Int'l Symp. on Quality Electronic Design (ISQED), 2020, pp. 40-45 [PDF]

29. H. Salmani, M. Yasin, J. Rajendran, T. Hoque, S. Bhunia, N. Karimi , "Countering IP Security threats in Supply chain," Proc. IEEE VLSI Test Symp. (VTS), 2019, pp.1-9 [PDF]

28. N. Karimi , S. Guilley, and J. Danger, "Impact of Aging on Template Attacks," Proc. ACM Great Lakes Symp. on VLSI (GlSVLSI), 2018, pp. 455-458 [PDF]

27. N. Karimi , J. Danger, and S. Guilley, "On the Effect of Aging in Detecting Hardware Trojan Horses with Template Analysis," Proc. IEEE Int'l Symp. on On-Line Testing and Robust System Design (IOLTS), 2018, pp. 281-286 [PDF]

26. J. Shey, N. Karimi , R. Robucci, and C. Patel, "Design-Based Fingerprinting Using Side-Channel Power Analysis for Protection Against IC Piracy," Proc. IEEE Computer Society Annual Symp. on VLSI (ISVLSI), 2018, pp. 614-619 [PDF]

25. D.Kraak, M. Taouil, S. Hamdioui, P.Weckx, F. Catthoor, A. Singh, A. Chatterjee, H.-J.Wunderlich, and N. Karimi , "Device Aging: A Security and Reliability Concern," Proc. IEEE European Test Symp. (ETS), 2018, pp. 1-10 [PDF]

24. N. Karimi , J. Danger, M. Slimani, and S. Guilley, "Impact of the Switching Activity on the Aging of Delay-PUFs," Proc. IEEE European Test Symp. (ETS), 2017, pp. 1-2 [PDF]

23. N. Karimi , J. Danger, F. Lozac'h, and S. Guilley, "Predictive Aging of Reliability of two Delay PUFs," Proc. Int'l Conf. on Security, Privacy and Applied Cryptographic Engineering (SPACE), vol. 9, no. 5, 2016, pp. 571–586 [PDF]

22. N. Karimi and K. Huang, "Prognosis of NBTI Aging Using a Machine Learning Scheme," Proc. Int'l Symp. on Defect and Fault Tolerance of VLSI Systems (DFTS), 2016 [PDF]

21. X. Guo, N. Karimi , F. Regazzoni, C.Jin, and R. Karri, "Simulation and Analysis of Negative-Bias Temperature Instability Aging on Power Analysis Attacks," Proc. Hardware-Oriented Security and Trust Symp. (HOST), 2015, pp. 124-129 [PDF]

20. A. DeTrano, S. Guilley, X. Guo, N. Karimi , R. Karri, "Exploiting Small Leakages in Masks to Turn a Second-Order Attack into a First-Order Attack," Proc. Hardware and Architectural Support for Security and Privacy (HASP), 2015, pp. 7:1-7:5 [PDF]

19. S. Kannan, N. Karimi , and O. Sinanoglu, "Secure memristor-based main memory," Proc. Design Automation Conf. (DAC), 2014, pp. 1-6 [PDF]

18. S. Kannan, N. Karimi , R. Karri, and O. Sinanoglu, "Detection, diagnosis, and repair of faults in memristor-based memories," Proc. VLSI Test Symp. (VTS), 2014, pp. 1-6 [PDF]

17. O. Sinanoglu, N. Karimi , J. Rajendran, R. Karri, Y. Jin, K. Huang, and Y. Makris, "Reconciling the IC test and security dichotomy," Proc. European Test Symp. (ETS), 2013, pp. 1-6 [PDF]

16. N. Karimi , K. Chakrabarty, P. Gupta, and S. Patil, "Test generation for clock domain crossing faults in integrated circuits," Proc. Design Automation & Test in Europe Conf. (DATE), 2012, pp. 406-411 [PDF]

15. N. Karimi , Z. Kong, K. Chakrabarty, P. Gupta, and S. Patil, "Testing of clock-domain crossing faults in multi-core system-on-chip," Proc. Asian Test Symp. (ATS), 2011, pp. 7-14 [PDF]

14. N. Karimi , S. Sadeghi, and Z. Navabi, "Network-on-chip concurrent error recovery using functional switch faults," Proc. Workshop on RTL and High Level Testing (WRTLT), 2010

13. N. Karimi , M. Maniatakos, C. Tirumurti, A. Jas, and Y. Makris, "Impact analysis of performance faults in modern microprocessors," Proc. Int'l. Conf. on Computer Design (ICCD), 2009, pp. 91-96 [PDF]

12. M. Maniatakos, N. Karimi , C. Tirumurti, A. Jas, and Y. Makris, "Instruction-level impact comparison of RT- vs. gate-level faults in a modern microprocessor controller," Proc. VLSI Test Symp. (VTS), 2009, pp. 9-14 [PDF]

11. N. Karimi , M. Maniatakos, Y. Makris, and A. Jas, "On the correlation between controller faults and instruction-level errors in modern microprocessors," Proc. Int'l. Test Conf. (ITC), 2008, pp. 24.1.1-24.1.10 [PDF]

10. A. Alaghi, M. Sedghi, N. Karimi , and Z. Navabi, "NoC reconfiguration for utilizing the largest fault-free connected sub-structure," Proc. Int'l. Test Conf. (ITC), 2008, pp.1-1 [PDF]

9. M. Maniatakos, N. Karimi , Y. Makris, A. Jas, and C. Tirumurti, "Design and evaluation of a timestamp-based concurrent error detection method (CED) in a modern microprocessor controller," Proc. Int'l Symp. on Defect and Fault Tolerance of VLSI Systems (DFTS), 2008, pp. 454-462 [PDF]

8. A. Alaghi, M. Sedghi, N. Karimi , M. Fathy, and Z. Navabi, "Reliable NoC architecture utilizing a robust rerouting algorithm," Proc. Int'l East-West Design and Test Symp. (EWDTS), 2008, pp. 200-203 [PDF]

7. N. Karimi , S. Aminzadeh, S. Safari, and Z. Navabi, "A Novel GA-based high-level synthesis technique to enhance RT-level concurrent testing," Proc. Int'l. Online Test Symp. (IOLTS), 2008, pp. 173-174 [PDF]

6. A. Alaghi, N. Karimi , M. Sedghi, and Z. Navabi, "Online NoC switch fault detection and diagnosis using a high level fault model," Proc. Int'l. Symp. on Defect and Fault Tolerance of VLSI Systems (DFTS), 2007, pp. 21-30 [PDF]

5. N. Karimi , S. Mirkhani, Z. Navabi, and F. Lombardi, "RT level reliability enhancement by constructing dynamic TMRs," Proc. ACM Great Lakes Symp. on VLSI (GlSVLSI), 2007, pp. 172-175 [PDF]

4. N. Karimi , and Z. Navabi, "A dynamic reconfiguration method for error recovery of RT level designs," Proc. Int'l. East-West Design and Test Symp. (EWDTS), 2007, pp. 249-254

3. N. Karimi , S. Mirkhani, and Z. Navabi, "ESTA: An efficient method for reliability enhancement of RT-Level designs," Proc. Asian Test Symp. (ATS), 2006, pp. 195-202 [PDF]

2. N. Karimi , P. Riahi, and Z. Navabi, "A survey of testability measurements at various abstraction levels," Proc. North Atlantic Test Workshop (NATW), 2003, pp. 26- 33 [PDF]

1. P. Riahi, Z. Navabi, N. Karimi , and F. Lombardi, "A VPI-based IP core serial fault simulation and test generation methodology," Proc. North Atlantic Test Workshop (NATW), 2003, pp. 96-103 [link]