UMBC CMSC 313, Computer Organization & Assembly Language, Spring 2002, Section 0101

Flip-Flops

Thursday 04/18, 2001

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Assigned Reading in Murdocca & Heuring:  A.11

Assigned Reading in Neveln:   

Assigned:   

Due:   

Topics Covered:

• Introduction to sequential logic.
• A model of a finite state machine with flip-flops acting acting as memory elements.
• The basic idea of a latch illustrated with a relay and with two inverters.
• An SR flip-flop (latch) constructed from two NOR gates and from two NAND gates.
• Using a clock to solve the problem of glitches and hazards.
• Clocked SR flip-flops and clocked D flip-flops.
• Some timing issues solved with a master-slave D flip-flop.
• Clocked J-K flip-flops and the endless toggle problem.

Circuits in DigSim:

Following these links will launch the DigSim Java applet and load the circuit described.

• An SR flip-flop
• A clocked SR flip-flop
• D flip-flop
• Master-Slave D flip-flop
• JK flip-flop