UMBC CMSC 313, Computer Organization & Assembly Language, Fall 2003, Section 0101

Flip Flops I

Tuesday 11/11, 2001

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Assigned Reading in Murdocca & Heuring:  A.11

Assigned Reading in Neveln:   

Assigned:   

Due:   

Topics Covered:

• Slides are available in PDF: Slides21.pdf
• Higher dimensional Karnaugh maps (and why they are awkward).
• Quine-McCluskey tabular algorithm for circuit minimization.
• Introduction to Sequential Logic.
• An SR latch.
• Hazards & glitches and why we need clocks.
• A clocked S-R latch, a clocked D latch, and a master-slave D flip-flop.

Circuits in DigSim:

Following these links will launch the DigSim Java applet and load the circuit described.

• An SR flip-flop
• A clocked SR flip-flop
• D flip-flop
• Master-Slave D flip-flop