UMBC CMSC 313, Computer Organization & Assembly Language, Fall 2003, Section 0101

Circuits for Addition

Tuesday 10/28, 2001

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Assigned Reading in Murdocca & Heuring:  3.5

Assigned Reading in Neveln:   

Assigned:   

Due:   

Topics Covered:

• Slides are available in PDF: Slides17.pdf
• Design of a half adder and a full adder. Considered the trade-offs between speed (lower propagation delay) and size (number of gates).
• Using 4 full adders to construct a 4-bit ripple carry adder.
• A 4-bit carry-lookahead adder.
• A combined adder/subtractor is possible for two's complement numbers.
• Midterm exam returned and discussed.

Circuits in DigSim:

Following these links will launch the DigSim Java applet and load the circuit described.

• A Half Adder that follows the SOP formula derived from the truth table for a half adder.
• A Half Adder using an XOR gate.
• A Full Adder using simplified Boolean formulas.
• A Full Adder using two half adders.