bitvec instrmemaddr instrmemaddr_*
bitvec instrmemdata instrmemdata_*
bitvec wbdata wbdata_*
bitvec wbaddr wbaddr_*
bitvec result result_*
bitvec addres addres_*
bitvec npc npc_*
bitvec c c_*
bitvec ir ir_*
bitvec instr_out instr_out_*
bitvec hzdec0/t1 hzdec0/t1_*
bitvec hzdec0/t2 hzdec0/t2_*
watch wbenable dlxclock dlxreset instrmemwren stall if_id_reset
watch hzdec0/alu_t  hzdec0/ld_t
watch controlpc
watch adderen
watch hzdec0/all_0_bar
bitvec branchpc branchpc_*
hi pcreset
hi dlxreset 
hi dlxclock
hi wbenable
hi instrmemwren
clock dlxclock 01
stepsize 100
sbvec wbaddr 00000
sbvec wbdata 00000000000000000000000000000000
cl
sbvec wbaddr 00001
sbvec wbdata 00000000000000000000000000000010
cl
sbvec wbaddr 00010
sbvec wbdata 00000000000000000000000000000110
cl
sbvec wbaddr 00011
sbvec wbdata 00000000000000000000000000000011
cl
sbvec wbaddr 00100
sbvec wbdata 00000000000000000000000000000111
cl

sbvec instrmemaddr 00000
sbvec instrmemdata 10000000000000010000000000000100
cl 
sbvec instrmemaddr 00001
sbvec instrmemdata 11110000000000000000000000000010
cl
sbvec instrmemaddr 00010
sbvec instrmemdata 10000000000000010000000000000100
cl 
sbvec instrmemaddr 00100
sbvec instrmemdata 10000000001000100000000000000111
cl
sbvec instrmemaddr 00101
sbvec instrmemdata 10000000011001000000000000000100
cl

lo instrmemwren
lo pcreset
lo dlxreset
lo wbenable



