// mult_20x20.v
//
// 20 x 20-bit signed pipelined multiplier
//    Inputs and outputs are registered
//
// 2004/03/09  Written

`timescale 10ps/1ps
`celldefine
module mult_20x20 (
   ina,
   inb,
   out,
   clk
   );

   input  signed [19:0]         ina;
   input  signed [19:0]         inb;
   input                        clk;

   output signed [39:0]         out;


   //----- declarations
   reg  signed [19:0]           r_ina;
   reg  signed [19:0]           r_inb;
   wire signed [39:0]           c_out;
   reg  signed [39:0]           out;
   

   //----- main
   assign c_out = r_ina * r_inb;

   always @(posedge clk) begin
      r_ina   <= #1 ina;
      r_inb   <= #1 inb;
      out     <= #1 c_out;
   end


endmodule  // mult_20x20
`endcelldefine