// mem_64x40.v
//
// 64 word by 40-bit, 2-read port + 2-write port memory
//
// 2004/03/09  Written

`timescale 10ps/1ps
`celldefine
module mem_64x40 (
   addrw0,
   dataw0,
   wren0,
   addrw1,
   dataw1,
   wren1,
   addrr0,
   datar0,
   addrr1,
   datar1,
   clk
   );

   input  [5:0]		addrw0;
   input  [5:0]		addrw1;
   input  [5:0]		addrr0;
   input  [5:0]		addrr1;
   input  [39:0]        dataw0;
   input  [39:0]        dataw1;
   output [39:0]        datar0;
   output [39:0]        datar1;
   input                wren0;           // write if high
   input                wren1;           // write if high
   input                clk;


   //----- declarations
   reg    [39:0]        mem_array [0:63]; 

   wire   [5:0]		addrw0;
   wire   [5:0]		addrw1;
   wire   [5:0]		addrr0;
   wire   [5:0]		addrr1;
   wire   [39:0]        dataw0;
   wire   [39:0]        dataw1;
   reg    [39:0]        datar0;
   reg    [39:0]        datar1;
   wire                 wren0;           // write if high
   wire                 wren1;           // write if high
   

   //----- main
   always @(posedge clk) begin
      if (wren0)  mem_array[addrw0]   <= #1 dataw0;
      if (wren1)  mem_array[addrw1]   <= #1 dataw1;
      datar0                          <= #1 mem_array[addrr0];
      datar1                          <= #1 mem_array[addrr1];
   end

endmodule  // mem_64x40
`endcelldefine