// fft.v
//
// FFT processor (w/o memory)
//
// 2004/03/09  Written

`timescale 10ps/1ps
`celldefine
module fft (
   reset,
   clk,
   in_real,
   in_imag,
   hold_in,
   addrw0,
   dataw0,
   wren0,
   addrw1,
   dataw1,
   wren1,
   addrr0,
   datar0,
   addrr1,
   datar1,
   out_real,
   out_imag,
   valid,
   multa0,
   multa1,
   multaprod,
   multb0,
   multb1,
   multbprod,
   multc0,
   multc1,
   multcprod,
   multd0,
   multd1,
   multdprod
   );

   // general signals
   input                reset; 
   input                clk;

   // input interface
   input  [19:0]        in_real;
   input  [19:0]        in_imag;
   output               hold_in;

   // memory interface
   output [5:0]         addrw0;
   output [5:0]         addrw1;
   output [5:0]         addrr0;
   output [5:0]         addrr1;
   output [39:0]        dataw0;
   output [39:0]        dataw1;
   input  [39:0]        datar0;
   input  [39:0]        datar1;
   output               wren0;           // write if high
   output               wren1;           // write if high

   // output interface
   output  [19:0]       out_real;
   output  [19:0]       out_imag;
   output               valid;

   // multiplier interface
   output  [19:0]       multa0;
   output  [19:0]       multa1;
   input   [39:0]       multaprod;
   output  [19:0]       multb0;
   output  [19:0]       multb1;
   input   [39:0]       multbprod;
   output  [19:0]       multc0;
   output  [19:0]       multc1;
   input   [39:0]       multcprod;
   output  [19:0]       multd0;
   output  [19:0]       multd1;
   input   [39:0]       multdprod;


   //----- declarations
   reg                  hold_in;
   reg    [5:0]         addr;
   reg                  wren;
   reg    [39:0]        dataw;
   reg    [19:0]        out_real;
   reg    [19:0]        out_imag;
   reg    [19:0]        c_out_real;
   reg    [19:0]        c_out_imag;
   reg                  valid;
   reg                  c_valid;
   reg    [2:0]         state;
   reg    [2:0]         c_state;

   reg                  c_hold_in;
   reg    [7:0]         count;
   reg    [7:0]         c_count;

   wire    [19:0]       multa0;
   wire    [19:0]       multa1;
   wire    [39:0]       multaprod;
   wire    [19:0]       multb0;
   wire    [19:0]       multb1;
   wire    [39:0]       multbprod;
   wire    [19:0]       multc0;
   wire    [19:0]       multc1;
   wire    [39:0]       multcprod;
   wire    [19:0]       multd0;
   wire    [19:0]       multd1;
   wire    [39:0]       multdprod;
   assign multa0 = in_real;     // temp hack!
   assign multa1 = in_imag;     // temp hack!
   

   //----- main
   always @(count or state or reset or out_real or out_imag) begin
      // defaults
      c_hold_in   = 1'b1;
      c_count     = count + 8'h01;
      c_state     = state;
      c_valid     = 1'b0;
      c_out_real  = out_real;
      c_out_imag  = out_imag;

      case (state)
         // reset; stay in reset state a few cycles after the "reset" signal
         //    is de-asserted like we discussed in lecture to reduce the 
         //    number of FFs that need to be reset.
         3'h0: begin
            if (count == 8'h04) begin
               c_state    = 3'h1;
               c_count    = 8'h00;
               c_hold_in  = 1'b0;
               end
            end

         // load data
         3'h1: begin
            c_hold_in   = 1'b0;

            if (count == 8'd63) begin
               c_state    = 3'h2;
               c_count    = 8'h00;
               c_hold_in  = 1'b1;
               end
            end

         // do fft...
         3'h2: begin
            if (count == 8'd200) begin
               c_state    = 3'h3;
               c_count    = 8'h00;
               end
            end

         // dump fft state...
         3'h3: begin
            c_out_real  = count;   // hack
            c_out_imag  = count+1; // hack
            c_valid   = 1'b1;
            if (count == 8'd63) begin
               c_state    = 3'h4;
               c_count    = 8'h00;
               end
            end
      endcase

      if (reset) begin
         c_hold_in      = 1'b1;         // also above
         c_count        = 8'h00;
         c_state        = 3'h0;
         c_valid        = 1'b0;         // also above
         end
   end


   // real registers
   always @(posedge clk) begin
      hold_in           <= #1 c_hold_in;
      count             <= #1 c_count;
      state             <= #1 c_state;
      valid             <= #1 c_valid;
      out_real          <= #1 c_out_real;
      out_imag          <= #1 c_out_imag;
   end


endmodule  // fft
`endcelldefine