// dsource.v
//
// Source of data with several different modes
//
// 2007/02/10  Added small magnitude random and freq=2 signals to test
//             block floating point.
// 2004/03/15  Removed excess variables from always sensitivity list.
// 2004/03/09  Written

`timescale 10ps/1ps
`celldefine
module dsource (
   mode,
   reset,
   hold,
   out_real,
   out_imag,
   clk
   );

   input  [7:0]         mode;
   input                reset;
   input                hold;           // pause if high, dump if low
   input                clk;

   output   [15:0]       out_real; // in 8.8 format
   output   [15:0]       out_imag; // in 8.8 format


   //----- declarations
   reg    signed[15:0]        out_real;
   reg    signed[15:0]        out_imag;
   reg    [5:0]         count;
   integer              r;
   integer              ChanDesc;
   integer              WritingFile;
	
	integer 					myFile;
   
//`ifdef XILINX_ISIM
   //----- main
   initial begin
      r                 = 123;          // random seed
      ChanDesc          = $fopen("datain.m");
		myFile				= $fopen("source.txt");
      $fwrite(ChanDesc, "%s", "% Note: data output in unsigned format and \n");
      $fwrite(ChanDesc, "%s", "%    must be converted to signed ");
      $fwrite(ChanDesc, "%s", " explicitly.\n%\n\n");
      WritingFile       = 1;
   end
//`endif

   always @(mode or count) begin
      case (mode)
      // positive real impulse at DC
      8'h00: begin
         out_real = 16'h0000;
         out_imag = 16'h0000;
         if (count == 6'h00)  out_real = {12'h7ff, 4'b0000};
         end

      // negative real impulse at DC
      8'h01: begin
         out_real = 16'h0000;
         out_imag = 16'h0000;
         if (count == 6'h00)  out_real = {12'h800, 4'b0000};
         end

      // positive real impulse at freq=1
      8'h02: begin
         out_real = 16'h0000;
         out_imag = 16'h0000;
         if (count == 6'h01)  out_real = {12'h7ff, 4'b0000};
         end

      // positive real impulse at freq=2
      8'h03: begin
         out_real = 16'h0000;
         out_imag = 16'h0000;
         if (count == 6'h02)  out_real = {12'h7ff, 4'b0000};
         end

      // positive real impulse at freq=3
      8'h04: begin
         out_real = 16'h0000;
         out_imag = 16'h0000;
         if (count == 6'h03)  out_real = {12'h7ff, 4'b0000};
         end

      // DC negative, real+imag
      8'h05: begin
         out_real = {16'h800, 4'b0000};
         out_imag = {16'h800, 4'b0000};
         end

      // rect input.  max positive for 0 - 5 and (N-5) - (N-1)
      // Make sure you verify this is correct for the value of N!
      8'h06: begin
         out_real = 16'h0000;
         out_imag = 16'h0000;
         if (count <= 6'd05 || count >= 6'd59)  
            out_real = {12'h7ff, 4'b0000};
         end
//`ifdef XILINX_ISIM
      // random
      8'h07: begin
         r = $random(r);
            out_real = {r[15:4],    // mantissa
            r[1], r[1], r[1:0]};    // exponent = {-2, -1, 0, +1}
         r = $random(r);
            out_imag = {r[15:4],    // mantissa
            r[1], r[1], r[1:0]};    // exponent = {-2, -1, 0, +1}
         end

      // small random.  Replicate MSB sign bit to necessary width.
      8'h08: begin
         r = $random(r);
            out_real = {r[7], r[7], r[7], r[7], r[7:0],   // mantissa
            4'b0000};                                     // exponent
         r = $random(r);
            out_imag = {r[7], r[7], r[7], r[7], r[7:0],   // mantissa
            4'b0000};                                     // exponent
         end
//`endif

      // small positive real impulse at freq=2
      8'h09: begin
         out_real = 16'h0000;
         out_imag = 16'h0000;
         if (count == 6'h02)  out_real = {12'h010, 4'b0000};
         end

      default: begin
         $write("Error: default case unexpected\n\n");
         end
      endcase
   end


   // count control variable
   always @(posedge clk) begin
      if (reset)
         count    <= #1 0;
      else if (hold)
         count    <= #1 count;
      else begin
//`ifdef XILINX_ISIM
         if (WritingFile) begin
            $fwrite(ChanDesc, "in(%0d)=%0d +", count+1, out_real);
            $fwrite(ChanDesc, " i*%0d;\n", out_imag);
				$fwrite(myFile, "%b\n%b\n", out_real, out_imag);
         end
         if (count == 15) begin
            $fclose(ChanDesc);
				$fclose(myFile);
            WritingFile  = 0;
         end
//`endif
         count    <= #1 count + 1;
      end
   end

endmodule  // dsource
`endcelldefine