// dsink.v
//
// Receives and logs data 
//
// 2004/03/09  Written

`timescale 10ps/1ps
`celldefine
module dsink (
   reset,
   in_real,
   in_imag,
   valid,
   clk
   );

   input                reset;
   input  [15:0]        in_real;
   input  [15:0]        in_imag;
   input                valid;
   input                clk;


   //----- declarations
   wire   signed [15:0]        in_real;
   wire   signed [15:0]        in_imag;
   reg    [5:0]         count;
   integer              ChanDesc;
   integer              WritingFile;
	integer					myFile;
   
//`ifdef XILINX_ISIM
   //----- main
   initial begin
      ChanDesc          = $fopen("dataout.m");
		myFile				= $fopen("sink.txt");
      $fwrite(ChanDesc, "%s", "% Note: data output in unsigned format and \n");
      $fwrite(ChanDesc, "%s", "%    must be converted to signed ");
      $fwrite(ChanDesc, "%s", " explicitly.\n%\n\n");
      WritingFile       = 1;
   end
//`endif

   // count control variable
   always @(posedge clk) begin
      if (reset)
         count    <= #1 0;
      else if (valid == 1'b0)
         count    <= #1 count;
      else begin
//`ifdef XILINX_ISIM		
         if (WritingFile) begin
            $fwrite(ChanDesc, "out(%0d)=%0d +", count+1, in_real);
            $fwrite(ChanDesc, " i*%0d;\n", in_imag);
				$fwrite(myFile, "%b\n%b\n", in_real, in_imag);
         end
         if (count == 15) begin
            $fclose(ChanDesc);
				$fclose(myFile);
            WritingFile  = 0;
         end
//`endif				
         count    <= #1 count + 1;
      end
   end

endmodule  // dsink
`endcelldefine