// butter.vt
//
// Tester for butterfly unit  (untested!)
//
// 2006/03/06  W inputs should not be allowed to go greater than magnitude 1
// 2006/02/28  Written

`timescale 10ps/1ps
`celldefine
module butter_vt (
   );

   parameter    CLK_PHASE_TIME = 100;

   //----- declarations
   reg    [15:0]        Ar, Ai;
   reg    [15:0]        Br, Bi;
   reg    [15:0]        Wr, Wi;
   reg                  clk;

   wire   [15:0]        Xr, Xi;
   wire   [15:0]        Yr, Yi;

   integer              r;
   integer              count;
   integer              ChanDesc;
   

   //----- butterfly
   butter b (
      .Ar(Ar),
      .Ai(Ai),
      .Br(Br),
      .Bi(Bi),
      .Wr(Wr),
      .Wi(Wi),
      .Xr(Xr),
      .Xi(Xi),
      .Yr(Yr),
      .Yi(Yi),
      .clk(clk)
      );
   

   //----- main
   initial begin
      r                 = 123;          // random seed
      ChanDesc          = $fopen("datain.m");
      $fwrite(ChanDesc, "%s", "% Note: data output in unsigned format and \n");
      $fwrite(ChanDesc, "%s", "%    must be converted to signed ");
      $fwrite(ChanDesc, "%s", " explicitly.\n%\n\n");
   end

   //----- main
   initial begin
      $recordfile("butter_vt");   // name of output dump file
      $recordvars(butter);        // name of module whose signals are dumped
      count = 0;

      clk = 1'b0; #CLK_PHASE_TIME; clk = 1'b1; #CLK_PHASE_TIME;
      clk = 1'b0; #CLK_PHASE_TIME; clk = 1'b1; #CLK_PHASE_TIME;
      clk = 1'b0; #CLK_PHASE_TIME; clk = 1'b1; #CLK_PHASE_TIME;

      for (count = 0; count < 5; count = count+1) begin
         r = $random(r);  Ar = r[15:0];
         r = $random(r);  Ai = r[15:0];
         r = $random(r);  Br = r[15:0];
         r = $random(r);  Bi = r[15:0];
         r = $random(r);  Wr = {r[14], r[14:0]};  // limit mag of |W| <= 1
         r = $random(r);  Wi = {r[14], r[14:0]};  // limit mag of |W| <= 1
         clk = 1'b0; #CLK_PHASE_TIME; clk = 1'b1; #CLK_PHASE_TIME;
         $fwrite(ChanDesc, "A(%0d)=%0d + i*%0d;\n", count+1, Ar, Ai);
         $fwrite(ChanDesc, "B(%0d)=%0d + i*%0d;\n", count+1, Br, Bi);
         $fwrite(ChanDesc, "W(%0d)=%0d + i*%0d;\n", count+1, Wr, Wi);
         $fwrite(ChanDesc, "X(%0d)=%0d + i*%0d;\n", count+1, Xr, Xi);
         $fwrite(ChanDesc, "Y(%0d)=%0d + i*%0d;\n", count+1, Yr, Yi);
         count = count+1;
      end

      // Remember the last few outputs won't be read unless you flush out 
      // the pipline
      clk = 1'b0; #CLK_PHASE_TIME; clk = 1'b1; #CLK_PHASE_TIME;
      clk = 1'b0; #CLK_PHASE_TIME; clk = 1'b1; #CLK_PHASE_TIME;
      clk = 1'b0; #CLK_PHASE_TIME; clk = 1'b1; #CLK_PHASE_TIME;

      $fclose(ChanDesc);
      $finish;
   end

endmodule
`endcelldefine