Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:12.4 (ISE) - M.81d Target Family: Virtex5
OS Platform: NT Target Device: xc5vlx110t
Project ID (random number) f827a5221e5948d18b535edb8364c961.C15FB99411B645E38A94F55A6882294B.1 Target Package: ff1136
Registration ID 200314014_200316044_801 Target Speed: -1
Date Generated 2011-01-09T14:03:03 Tool Flow ISE
 
User Environment
OS Name Microsoft OS Release major release (build 7600)
CPU Name Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz CPU Speed 2394 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=1
  • 24-bit adder=1
Comparators=2
  • 24-bit comparator greater=2
Counters=2
  • 24-bit up counter=1
  • 4-bit up counter=1
Registers=1
  • Flip-Flops=1
MiscellaneousStatistics
  • AGG_BONDED_IO=6
  • AGG_IO=6
  • AGG_LOCED_IO=6
  • AGG_SLICE=14
  • NUM_BONDED_IOB=6
  • NUM_BSFULL=29
  • NUM_BSLUTONLY=24
  • NUM_BSUSED=53
  • NUM_BUFG=1
  • NUM_LOCED_IOB=6
  • NUM_LOGIC_O5ANDO6=24
  • NUM_LOGIC_O5ONLY=22
  • NUM_LOGIC_O6ONLY=6
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O6=22
  • NUM_SLICEL=14
  • NUM_SLICE_CARRY4=12
  • NUM_SLICE_CONTROLSET=2
  • NUM_SLICE_CYINIT=100
  • NUM_SLICE_FF=29
  • NUM_SLICE_UNUSEDCTRL=6
  • NUM_UNUSABLE_FF_BELS=3
NetStatistics
  • NumNets_Active=50
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEIN=17
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_CLKPIN=8
  • NumNodesOfType_Active_CNTRLPIN=8
  • NumNodesOfType_Active_DOUBLE=44
  • NumNodesOfType_Active_GENERIC=2
  • NumNodesOfType_Active_GLOBAL=6
  • NumNodesOfType_Active_HLONG=1
  • NumNodesOfType_Active_INPUT=95
  • NumNodesOfType_Active_IOBIN2OUT=2
  • NumNodesOfType_Active_IOBINPUT=4
  • NumNodesOfType_Active_IOBOUTPUT=6
  • NumNodesOfType_Active_OUTBOUND=33
  • NumNodesOfType_Active_OUTPUT=41
  • NumNodesOfType_Active_PADINPUT=4
  • NumNodesOfType_Active_PADOUTPUT=2
  • NumNodesOfType_Active_PENT=8
  • NumNodesOfType_Active_PINBOUNCE=26
  • NumNodesOfType_Active_PINFEED=105
  • NumNodesOfType_Active_VLONG=1
  • NumNodesOfType_Vcc_INPUT=46
  • NumNodesOfType_Vcc_KVCCOUT=6
  • NumNodesOfType_Vcc_PINFEED=46
SiteStatistics
  • BUFG-BUFGCTRL=1
  • IOB-IOBM=3
  • IOB-IOBS=3
  • SLICEL-SLICEM=6
SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • IOB=6
  • IOB_INBUF=2
  • IOB_OUTBUF=4
  • IOB_PAD=6
  • SLICEL=14
  • SLICEL_A5LUT=12
  • SLICEL_A6LUT=14
  • SLICEL_AFF=7
  • SLICEL_B5LUT=12
  • SLICEL_B6LUT=13
  • SLICEL_BFF=7
  • SLICEL_C5LUT=12
  • SLICEL_C6LUT=13
  • SLICEL_CARRY4=12
  • SLICEL_CFF=7
  • SLICEL_CYINITGND=1
  • SLICEL_D5LUT=10
  • SLICEL_D6LUT=13
  • SLICEL_DFF=8
 
Configuration Data
SLICEL
  • CLK=[CLK:8] [CLK_INV:0]
SLICEL_AFF
  • AFFINIT=[INIT0:7]
  • AFFSR=[SRLOW:7]
  • CK=[CK:7] [CK_INV:0]
  • LATCH_OR_FF=[FF:7]
  • SYNC_ATTR=[ASYNC:7]
SLICEL_BFF
  • BFFINIT=[INIT0:7]
  • BFFSR=[SRLOW:7]
  • CK=[CK:7] [CK_INV:0]
  • LATCH_OR_FF=[FF:7]
  • SYNC_ATTR=[ASYNC:7]
SLICEL_CFF
  • CFFINIT=[INIT0:7]
  • CFFSR=[SRLOW:7]
  • CK=[CK:7] [CK_INV:0]
  • LATCH_OR_FF=[FF:7]
  • SYNC_ATTR=[ASYNC:7]
SLICEL_DFF
  • CK=[CK:8] [CK_INV:0]
  • DFFINIT=[INIT0:8]
  • DFFSR=[SRLOW:8]
  • LATCH_OR_FF=[FF:8]
  • SYNC_ATTR=[ASYNC:8]
 
Pin Data
BUFG
  • I0=1
  • O=1
BUFG_BUFG
  • I0=1
  • O=1
IOB
  • I=2
  • O=4
  • PAD=6
IOB_INBUF
  • OUT=2
  • PAD=2
IOB_OUTBUF
  • IN=4
  • OUT=4
IOB_PAD
  • PAD=6
SLICEL
  • A=1
  • A4=7
  • A5=12
  • A6=13
  • AQ=7
  • AX=1
  • B4=7
  • B5=12
  • B6=13
  • BQ=7
  • C4=7
  • C5=13
  • C6=13
  • CIN=10
  • CLK=8
  • COUT=10
  • CQ=7
  • D3=1
  • D4=7
  • D5=11
  • D6=13
  • DMUX=1
  • DQ=8
  • SR=8
SLICEL_A5LUT
  • O5=12
SLICEL_A6LUT
  • A4=7
  • A5=12
  • A6=13
  • O6=14
SLICEL_AFF
  • CK=7
  • D=7
  • Q=7
  • SR=7
SLICEL_B5LUT
  • O5=12
SLICEL_B6LUT
  • A4=7
  • A5=12
  • A6=13
  • O6=13
SLICEL_BFF
  • CK=7
  • D=7
  • Q=7
  • SR=7
SLICEL_C5LUT
  • O5=12
SLICEL_C6LUT
  • A4=7
  • A5=13
  • A6=13
  • O6=13
SLICEL_CARRY4
  • CIN=10
  • CO3=10
  • CYINIT=2
  • DI0=12
  • DI1=12
  • DI2=12
  • DI3=10
  • O0=6
  • O1=6
  • O2=6
  • O3=7
  • S0=12
  • S1=12
  • S2=12
  • S3=12
SLICEL_CFF
  • CK=7
  • D=7
  • Q=7
  • SR=7
SLICEL_CYINITGND
  • 0=1
SLICEL_D5LUT
  • O5=10
SLICEL_D6LUT
  • A3=1
  • A4=7
  • A5=11
  • A6=13
  • O6=13
SLICEL_DFF
  • CK=8
  • D=8
  • Q=8
  • SR=8
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc5vlx110t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc5vlx110t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
bitgen 1 1 0 0 0 0 0
map 1 1 0 0 0 0 0
ngdbuild 1 1 0 0 0 0 0
par 1 1 0 0 0 0 0
trce 1 1 0 0 0 0 0
xst 2 2 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/tbench PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2011-01-09T13:19:34 PROP_intWbtProjectID=C15FB99411B645E38A94F55A6882294B
PROP_intWbtProjectIteration=1 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_selectedSimRootSourceNode_behav=work.tbench
PROP_AutoTop=true PROP_DevFamily=Virtex5
PROP_DevDevice=xc5vlx110t PROP_DevFamilyPMName=virtex5
PROP_DevPackage=ff1136 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-1 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=2
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=29 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1
NGDBUILD_NUM_INV=3 NGDBUILD_NUM_LUT1=23 NGDBUILD_NUM_LUT2=24 NGDBUILD_NUM_LUT3=2
NGDBUILD_NUM_LUT4=1 NGDBUILD_NUM_MUXCY=46 NGDBUILD_NUM_OBUF=4 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=25
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDC=29 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=3 NGDBUILD_NUM_LUT1=23 NGDBUILD_NUM_LUT2=24
NGDBUILD_NUM_LUT3=2 NGDBUILD_NUM_LUT4=1 NGDBUILD_NUM_MUXCY=46 NGDBUILD_NUM_OBUF=4
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=25
 
ISim Statistics
Xilinx HDL Libraries Used=
Fuse Resource Usage=904 ms, 112164 KB