top Project Status
Project File: counter.xise Parser Errors: No Errors
Module Name: top Implementation State: Placed and Routed
Target Device: xc5vlx110t-1ff1136
  • Errors:
No Errors
Product Version:ISE 12.4
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 29 69,120 1%  
    Number used as Flip Flops 29      
Number of Slice LUTs 53 69,120 1%  
    Number used as logic 52 69,120 1%  
        Number using O6 output only 6      
        Number using O5 output only 22      
        Number using O5 and O6 24      
    Number used as exclusive route-thru 1      
Number of route-thrus 23      
    Number using O6 output only 23      
Number of occupied Slices 14 17,280 1%  
Number of LUT Flip Flop pairs used 53      
    Number with an unused Flip Flop 24 53 45%  
    Number with an unused LUT 0 53 0%  
    Number of fully used LUT-FF pairs 29 53 54%  
    Number of unique control sets 2      
    Number of slice register sites lost
        to control set restrictions
3 69,120 1%  
Number of bonded IOBs 6 640 1%  
    Number of LOCed IOBs 6 6 100%  
Number of BUFG/BUFGCTRLs 1 32 3%  
    Number used as BUFGs 1      
Average Fanout of Non-Clock Nets 3.05      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Mar 2 11:03:55 2011001 Info (0 new)
Translation ReportCurrentWed Mar 2 11:04:17 2011000
Map ReportCurrentWed Mar 2 11:05:58 2011006 Infos (0 new)
Place and Route ReportCurrentWed Mar 2 11:07:47 2011000
Power Report     
Post-PAR Static Timing ReportCurrentWed Mar 2 11:08:39 2011002 Infos (0 new)
Bitgen ReportOut of DateSun Jan 9 14:03:00 2011001 Info (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateSun Jan 9 13:40:22 2011
WebTalk ReportOut of DateSun Jan 9 14:03:03 2011
WebTalk Log FileOut of DateSun Jan 9 14:03:25 2011

Date Generated: 03/02/2011 - 15:20:45