ncverilog: 06.11-s008: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
TOOL:	ncverilog	06.11-s008: Started on Feb 17, 2016 at 16:59:07 EST
ncverilog
	+access+r
	dff.v
	dff_tb.v
file: dff.v
	module worklib.dff:v
		errors: 0, warnings: 0
file: dff_tb.v
	module worklib.dff_tb:v
		errors: 0, warnings: 0
		Caching library 'worklib' ....... Done
	Elaborating the design hierarchy:
	Building instance overlay tables: .................... Done
	Generating native compiled code:
		worklib.dff:v <0x4307d498>
			streams:   2, words:   337
		worklib.dff_tb:v <0x138b73fc>
			streams:   7, words:  2998
	Loading native compiled code:     .................... Done
	Building instance specific data structures.
	Design hierarchy summary:
		             Instances  Unique
		Modules:             2       2
		Registers:           4       4
		Scalar wires:        4       -
		Always blocks:       4       4
		Initial blocks:      1       1
		Pseudo assignments:  3       3
	Writing initial simulation snapshot: worklib.dff_tb:v

Trying to check out license...
	Incisive_HDL_Simulator 6.1 - Failed
	NC_Verilog_Simulator 6.1 - Failed
	Affirma_NC_Simulator 6.1 - Failed
	Incisive_Design_Team_Simulator 6.1 - Failed
	Incisive_Enterprise_Simulator 6.1 - Failed
ncsim: *F,NOLICN: Unable to checkout license for the simulation. (flag - 2) 'lic_error -15'.
TOOL:	ncverilog	06.11-s008: Exiting on Feb 17, 2016 at 16:59:10 EST  (total: 00:00:03)
ncverilog: *E,SIMERR: Error during Simulation (status 2), exiting.
TOOL:	ncverilog	06.11-s008: Exiting on Feb 17, 2016 at 16:59:10 EST  (total: 00:00:03)