ncverilog: 06.11-s008: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
TOOL:	ncverilog	06.11-s008: Started on Feb 10, 2016 at 18:07:51 EST
ncverilog
	+access+r
	Eight_Bit_Multiplier.v
	Eight_Bit_Multiplier_tb.v
Loading snapshot worklib.Eight_Bit_Multiplier_tb:v .................... Done
ncsim> source /afs/umbc.edu/software/cadence/software_2008/IUS61/tools/inca/files/ncsimrc
ncsim> run
Test    0: in0= 00000111(7), in1= 00010101(  21), out= 0000000000000000(     0)

Test    0: in0= 00000111(7), in1= 00010101(  21), out= 0000000010010011(   147)

Test    1: in0= 00001110(14), in1= 11111101(  -3), out= 0000000010010011(   147)

Test    1: in0= 00001110(14), in1= 11111101(  -3), out= 1111111111010110(   -42)

Test    2: in0= 11111111(-1), in1= 11111101(  -3), out= 1111111111010110(   -42)

Test    2: in0= 11111111(-1), in1= 11111101(  -3), out= 0000000000000011(     3)

Simulation interrupted at 262942369 NS + 0
ncsim> exit
TOOL:	ncverilog	06.11-s008: Exiting on Feb 10, 2016 at 18:08:18 EST  (total: 00:00:27)