//TestBench for D flip flop module

module dff_tb();
reg d,clk,rst;
wire q;
dff d1(d,clk,rst,q);
always@(posedge clk)
$display("d=%b,clk=%b,rst=%b,q=%b\n",d,clk,rst,q);
initial
	begin
	clk=0;
	rst=0;
	d=0;
	#15 rst=1;d=1;
	#10 rst=0;d=1;

#500 $finish;
	end
always #5 clk=~clk;
always #50 d= ~d;
endmodule