// Author: Amey Kulkarni, EEHPC Lab, UMBC
// D Flip flop with Synchronous reset.
//This code is the part of NCVerilog Tutorial.pdf on eehpc website

module dff (d,clk,rst,q);
input d, clk,rst;
output reg q;
always@(posedge clk)
	begin
	if(rst==1'b1)q<=1;
	else q<=d;
	end
endmodule