# ####################################################################

#  Created by Encounter(R) RTL Compiler v09.10-s106_2 on Mon Feb 22 16:59:06 EST 2016

# ####################################################################

set sdc_version 1.7

set_units -capacitance 1000.0fF
set_units -time 1000.0ps

# Set the current design
current_design Eight_Bit_Multiplier

create_clock -name "clk" -add -period 1.0 -waveform {0.0 0.5} [get_ports clk]
set_clock_transition 0.4 [get_clocks clk]
set_clock_gating_check -setup 0.0 
set_wire_load_mode "top"
set_dont_use [get_lib_cells sc9tap_ch013n_base_hvt_tt_nominal_max_1p20v_25c/RF1R1WX1TH]
set_dont_use [get_lib_cells sc9tap_ch013n_base_hvt_tt_nominal_max_1p20v_25c/RF2R1WX1TH]
set_dont_use [get_lib_cells sc9tap_ch013n_base_hvt_tt_nominal_max_1p20v_25c/RFRDX1TH]
set_dont_use [get_lib_cells sc9tap_ch013n_base_hvt_tt_nominal_max_1p20v_25c/RFRDX2TH]
set_dont_use [get_lib_cells sc9tap_ch013n_base_hvt_tt_nominal_max_1p20v_25c/RFRDX4TH]