# Extra Credit 1

## CMSC 411 / Olano, Spring 2012

In class, we went over a 1-bit ALU supporting add, subtract, and, or, and xor operations. Here's a logic diagram for that ALU. We'd like to design an *alternate* ALU with control signals 000 = ADD, 001 = SUB, 010 = not A, 011 = not B, 100 = A, 101 = AND, 110 = OR, 111 = XOR. For SUB, assume two's complement, so subtract is A+~B+1.

- Write out the logic table, relating the six inputs (3 operation bits, plus Ain, Bin and Cin) to the two outputs (Result and Cout). A naive table would have 2
^{6}=64 entries, but you can condense it considerably by using don't care for some of the entries. For example, when the operation bits are 010, you don't care what Bin or Cin are.
- Create a logic diagram for Result and Cout in sum of products form. You can draw it in PLA form, as shown in Appendix C of the book.