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	Journals Securing Designs against Scan-Based Side Channel Attacks Jeremy Lee, Mohammad Tehranipoor, Chintan Patel and Jim Plusquellic IEEE Transactions on Dependable and Secure Computing, Volume 4, Number 4, pp. 325-336, October 2007 Quiescent-Signal Analysis: A Multiple Supply Pad I_DDQ Method Jim Plusquellic, Dhruva Acharyya, Abhishek Singh, Mohammad Tehranipoor and Chintan Patel IEEE Design and Test of Computers, Volume 23, Issue 4, pp. 278-293, April 2006 Defect Simulation Methodology for i_DDT Testing Abhishek Singh, Jim Plusquellic, Dhananjay Phatak and Chintan Patel Journal of Electronic Testing: Theory and Applications, Volume 22, Issue 3, pp. 255-272, June 2006 Defect Detection using Quiescent Signal Analysis Chintan Patel, Abhishek Singh and Jim Plusquellic Journal of Electronic Testing: Theory and Applications, Volume 21, Issue 5, pp. 463-483, October 2005 Defect Diagnosis using a Current Ratio based Quiescent Signal Analysis Model for Commercial Power Grids Chintan Patel, E. Staroswiecki, S. Pawar, D. Acharyya and Jim Plusquellic Journal of Electronic Testing, Theory and Applications, Volume 19, Issue 6, pp. 611-623, December 2003 Power Supply Transient Signal Analysis for Defect-Oriented Test Jim Plusquellic, Abhishek Singh, Chintan Patel and Anne Gattiker Transactions on Computer Aided Design, Volume 22, Number 3, March 2003 Conferences/Workshops Estimating Power Supply Noise and Analyzing it's Impact on Path Delay Sushmita Kadiyala Rao, Chaitra Sathyanarayana, Ajay Kallianpur, Ryan Robucci and Chintan Patel IEEE VLSI Test Symposium, pp. 276-281, April 2012 Analyzing the Impact of Power Supply Noise on Propagation Delay Sushmita Kadiyala Rao, Chaitra Sathyanarayana, Ryan Robucci and Chintan Patel IEEE International Workshop on Defect and Adaptive Test Analysis, September 2011 Current Flattening Circuit for DPA Countermeasure Ekarat Laohavaleeson and Chintan Patel IEEE International Symposium on Hardware-Oriented Security and Trust, 2010, pp. 118-123 On-Chip Power Supply Noise Measurements Ekarat Laohavaleeson and Chintan Patel IEEE International Workshop on Defect and Data Driven Testing, November 2009 Verification of Convolution Relation Between Sensitized Path's Gate Transients, Power Grid Impulse Response and Power Port Transients Reza M. Rad, Jim Pluquellic, Chintan Patel and Abhishek Singh IEEE International Workshop on Defect and Data Driven Testing, November 2009 Triangulating to a Defect's Physical Coordinates Using Multiple Supply Pad I_DDQs: Test Chip Results Jim Plusquellic, Dhruva Acharrya, Mohammad Tehranipoor and Chintan Patel International Symposium for Testing and Failure Analysis, November, 2006, pp 36-45 On-Chip Multi-Functional Process Tolerant Power Supply Noise Monitor Ekarat Laohavaleeson and Chintan Patel IEEE Defect and Current Based Testing Workshop, pp. 13-14, October 2006 Multiple Supply Pad I_DDQ-based Defect Detection Techniques Applied to Hardware Test Chips Jim Plusquellic, Dhruva Acharyya, Abhishek Singh, Mohammad Tehranipoor and Chintan Patel IEEE Defect and Current Based Testing Workshop, October 2006 Triangulating to a Defect's Physical Coordinates Using Multiple Supply Pad I_DDQs Jim Plusquellic, Dhruva Acharyya, Mohammad Tehranipoor and Chintan Patel North Atlantic Test Workshop, May 2006 Securing Scan Design Using Lock & Key Technique Jeremy Lee, Mohammad Tehranipoor, Chintan Patel and Jim Plusquellic IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 51-62, October 2005 Sensitivity Analysis of Quiescent Signal Analysis for Defect Detection Dhruva Acharyya, Abhishek Singh, Mohammad Tehranipoor, Chintan Patel and Jim Plusquellic Defect Based Test Workshop, pp. 3-10, April 2005 Defect Detection under Realistic Leakage Models using Multiple I_DDQ Measurements Chintan Patel, Abhishek Singh and Jim Plusquellic IEEE International Test Conference, pp. 319-328, November 2004 On-Chip Impulse Response Generation for Analog and Mixed-Signal Testing Abhishek Singh, Chintan Patel and Jim Plusquellic International Test Conference, 2004 Ontology-driven Adaptive Sensor Networks S. Avancha, C. Patel and A. Joshi Int. Conference on Mobile and Ubiquitous Systems: Networking and Services, 2004 Fault Simulation for Power Supply Transient Current (I_DDT) Testing: An Investigation Abhishek Singh, Chintan Patel and Jim Plusquellic VLSI Test Symposium, 2004 Comparison of Branching CORDIC Implementations Abhiskeh Singh, D. Phatak, T. Goff, M. Riggs, J. Plusquellic and Chintan Patel International Conference on Application-Specific Systems, Arch. & Processors, 2003 Diagnosis using Quiescent Signal Analysis on a Commercial Power Grid Chintan Patel, Ernesto Staroswiecki, Smita Pawar, Dhurva Acharyya and Jim Plusquellic EDFAS International Symposium for Testing and Failure Analysis, pp 713-722, November 2002 A Current Ratio Model for Defect Diagnosis using Quiescent Signal Analysis Chintan Patel, Ernesto Staroswiecki, Dhurva Acharyya, Smita Pawar, and Jim Plusquellic Defect-based Testing Workshop at VLSI Test Symposium, April 2002 Power Supply Transient Signal Integration Circuit Chintan Patel, Fidel Muradali and Jim Plusquellic IEEE International Test Conference, pp. 395-404, October 2001 Detecting Delay Faults using Power Supply Transient Signal Analysis Abhishek Singh, Chintan Patel, Shirong Liao, Jim Plusquellic and Anne Gattiker IEEE International Test Conference, pp. 704-712, October 2001 A Process and Technology-Tolerant I_DDQ Method for IC Diagnosis Chintan Patel and Jim Plusquellic IEEE VLSI Test Symposium, pp. 145-150, April 2001 Predicting Device Performance From Pass/Fail Transient Signal Analysis Data Jim Plusquellic, Amy Germida, Jonathan Hudson, Ernesto Staroswiecki and Chintan Patel IEEE International Test Conference, pp. 1070-1079, October 2000 Quiescent Signal Analysis for IC Diagnosis Jim Plusquellic, Chintan Patel, and Ying Ouyang System Test and Diagnosis Workshop at ITC, October 2000
Copyright © 2005 Chintan Patel. Last updated on Jan 31, 2017.