UMBC CMSC 313, Computer Organization & Assembly Language, Spring 2002, Section 0101

Circuit Simplification I

Tuesday 04/30, 2001

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Assigned Reading in Murdocca & Heuring:  B.1-B.2

Assigned Reading in Neveln:   

Assigned:  HW5

Due:  DigSim2

Topics Covered:

• Change in plans: Homework 5 is assigned instead of DigSim Assignment 3. DigSim 3 will be assigned the following week.
• Using Karnaugh maps to simplify combinational logic circuits.
• Karnaugh maps find the smallest circuit in SOP or POS form.
• Here "smallest" means the smallest number of minterms (for SOP) and, among the formulas with the same number of minterms, the smallest number of factors in the minterms.
• There may be smaller circuits with more than 2 levels. Also, for functions with multiple bits of output, minimization should consider common subexpressions in the formulas for each bit of output. Karnaugh maps do not do this.
• In general circuit minimization is a hard problem (e.g., harder than cracking passwords).